vcu118: Add jtag flow control

Author: CyrilKoe

target/xilinx/flavor_bd/constraints/vcu118.xdc

@@ -23,6 +23,10 @@ set_property PACKAGE_PIN AW25     [get_ports "uart_tx_o"] ;# Bank  64 VCCO - VCC
 set_property IOSTANDARD  LVCMOS18 [get_ports "uart_tx_o"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64
 set_property PACKAGE_PIN BB21     [get_ports "uart_rx_i"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64
 set_property IOSTANDARD  LVCMOS18 [get_ports "uart_rx_i"] ;# Bank  64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64
+set_property PACKAGE_PIN BB22     [get_ports "uart_rts_o"] ;
+set_property IOSTANDARD  LVCMOS18 [get_ports "uart_rts_o"] ;
+set_property PACKAGE_PIN AY25     [get_ports "uart_cts_i"] ;
+set_property IOSTANDARD  LVCMOS18 [get_ports "uart_cts_i"] ;
 
 set_property PACKAGE_PIN L19      [get_ports cpu_reset] ;# Bank  73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73
 set_property IOSTANDARD  LVCMOS12 [get_ports cpu_reset] ;# Bank  73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73

target/xilinx/flavor_bd/flavor_bd.mk

@@ -49,6 +49,6 @@ $(CAR_XIL_DIR)/flavor_bd/out/%.bit: $(xilinx_ips_paths_bd) $(CAR_XIL_DIR)/flavor
 .PRECIOUS: $(CAR_XIL_DIR)/flavor_bd/out/%.bit
 
 car-xil-clean-bd:
-	cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_$(XILINX_BOARD) .Xil/
+	cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_* .Xil/
 
 .PHONY: car-xil-clean-bd

target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl

@@ -233,6 +233,8 @@ proc create_root_design { parentCell } {
    CONFIG.POLARITY {ACTIVE_LOW} \
  ] $pcie_perstn
   set phy_reset_out [ create_bd_port -dir O -from 0 -to 0 -type rst phy_reset_out ]
+  set uart_cts_i [ create_bd_port -dir I uart_cts_i ]
+  set uart_rts_o [ create_bd_port -dir O uart_rts_o ]
   set uart_rx_i [ create_bd_port -dir I uart_rx_i ]
   set uart_tx_o [ create_bd_port -dir O uart_tx_o ]