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CyrilKoeCyrilKoe
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fpga: Adding vcu118 BD support
1 parent 48185f6 commit 9c83de6

14 files changed

+688
-13
lines changed

‎sw/boot/carfield_bd_vcu128.dts ‎sw/boot/carfield_bd.dts

File renamed without changes.

‎sw/boot/carfield_vanilla_vcu128.dts ‎sw/boot/carfield_vanilla.dts

File renamed without changes.

‎target/xilinx/flavor_bd/constraints/vcu118.xdc

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# Copyright 2024 ETH Zurich and University of Bologna.
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# Solderpad Hardware License, Version 0.51, see LICENSE for details.
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# SPDX-License-Identifier: SHL-0.51
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#
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# Cyril Koenig <[email protected]>
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# VIOs are asynchronous
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set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}]
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# Create system clocks
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create_clock -period 4 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT]
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins design_1_i/util_ds_buf_0/IBUF_OUT]
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create_clock -period 10 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
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create_clock -period 10 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]]
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]]
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
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# PCIe clock LOC
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#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]]
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#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]]
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set_property PACKAGE_PIN AW25 [get_ports "uart_rx_i"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64
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set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64
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set_property PACKAGE_PIN BB21 [get_ports "uart_tx_o"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64
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set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64
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#set_property PACKAGE_PIN BB22 [get_ports "uart_rts_o"] ;
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#set_property IOSTANDARD LVCMOS18 [get_ports "uart_rts_o"] ;
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#set_property PACKAGE_PIN AY25 [get_ports "uart_cts_i"] ;
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#set_property IOSTANDARD LVCMOS18 [get_ports "uart_cts_i"] ;
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set_property PACKAGE_PIN L19 [get_ports cpu_reset] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73
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set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73
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set_property BOARD_PART_PIN default_250mhz_clk1_n [get_ports default_250mhz_clk1_clk_n]
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set_property BOARD_PART_PIN default_250mhz_clk1_p [get_ports default_250mhz_clk1_clk_p]
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set_property PACKAGE_PIN D12 [get_ports default_250mhz_clk1_clk_n] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71
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set_property IOSTANDARD DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_n] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71
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set_property PACKAGE_PIN E12 [get_ports default_250mhz_clk1_clk_p] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71
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set_property IOSTANDARD DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_p] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71

‎target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc

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# Copyright 2024 ETH Zurich and University of Bologna.
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# Solderpad Hardware License, Version 0.51, see LICENSE for details.
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# SPDX-License-Identifier: SHL-0.51
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#
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# Cyril Koenig <[email protected]>
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#
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set_property PACKAGE_PIN N30 [get_ports jtag_tdo_o]
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set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdo_o]
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set_property PACKAGE_PIN P30 [get_ports jtag_tck_i]
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set_property IOSTANDARD LVCMOS12 [get_ports jtag_tck_i]
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set_property PACKAGE_PIN N28 [get_ports jtag_tms_i]
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set_property IOSTANDARD LVCMOS12 [get_ports jtag_tms_i]
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set_property PACKAGE_PIN M30 [get_ports jtag_tdi_i]
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set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdi_i]

‎target/xilinx/flavor_bd/constraints/vcu118_hyperbus.xdc

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# Copyright 2024 ETH Zurich and University of Bologna.
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# Solderpad Hardware License, Version 0.51, see LICENSE for details.
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# SPDX-License-Identifier: SHL-0.51
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#
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# Cyril Koenig <[email protected]>
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O]
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# (FMCP_HSPC_LA13_N)
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set_property PACKAGE_PIN AJ36 [get_ports "pad_hyper_csn[1]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43
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# (FMCP_HSPC_LA13_P)
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set_property PACKAGE_PIN AJ35 [get_ports "pad_hyper_csn[0]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43
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# (FMCP_HSPC_LA14_P)
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set_property PACKAGE_PIN AG31 [get_ports "pad_hyper_rwds"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43
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# (FMCP_HSPC_LA09_N)
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set_property PACKAGE_PIN AK33 [get_ports "pad_hyper_dq[2]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[2]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43
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# (FMCP_HSPC_LA10_N)
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set_property PACKAGE_PIN AR35 [get_ports "pad_hyper_dq[3]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[3]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43
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# (FMCP_HSPC_LA10_P)
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set_property PACKAGE_PIN AP35 [get_ports "pad_hyper_dq[0]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43
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# (FMCP_HSPC_LA09_P)
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set_property PACKAGE_PIN AJ33 [get_ports "pad_hyper_dq[4]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[4]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43
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# (FMCP_HSPC_LA06_N)
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set_property PACKAGE_PIN AT36 [get_ports "pad_hyper_dq[7]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[7]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43
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# (FMCP_HSPC_LA06_P)
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set_property PACKAGE_PIN AT35 [get_ports "pad_hyper_dq[1]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[1]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43
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# (FMCP_HSPC_LA01_CC_N)
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set_property PACKAGE_PIN AL31 [get_ports "pad_hyper_ckn"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43
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# (FMCP_HSPC_LA01_CC_P)
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set_property PACKAGE_PIN AL30 [get_ports "pad_hyper_ck"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43
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# (FMCP_HSPC_LA05_N)
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set_property PACKAGE_PIN AR38 [get_ports "pad_hyper_dq[5]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43
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# (FMCP_HSPC_LA05_P)
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set_property PACKAGE_PIN AP38 [get_ports "pad_hyper_dq[6]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[6]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43

‎target/xilinx/flavor_bd/constraints/vcu128.xdc

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# Copyright 2024 ETH Zurich and University of Bologna.
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# Solderpad Hardware License, Version 0.51, see LICENSE for details.
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# SPDX-License-Identifier: SHL-0.51
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#
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# Cyril Koenig <[email protected]>
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# VIOs are asynchronous
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set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}]
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‎target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc

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# Copyright 2020 ETH Zurich and University of Bologna.
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# Copyright 2024 ETH Zurich and University of Bologna.
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# Solderpad Hardware License, Version 0.51, see LICENSE for details.
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# SPDX-License-Identifier: SHL-0.51
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#

‎target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc

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# Copyright 2020 ETH Zurich and University of Bologna.
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# Copyright 2024 ETH Zurich and University of Bologna.
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# Solderpad Hardware License, Version 0.51, see LICENSE for details.
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# SPDX-License-Identifier: SHL-0.51
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#

‎target/xilinx/flavor_bd/flavor_bd.mk

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@@ -49,6 +49,6 @@ $(CAR_XIL_DIR)/flavor_bd/out/%.bit: $(xilinx_ips_paths_bd) $(CAR_XIL_DIR)/flavor
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.PRECIOUS: $(CAR_XIL_DIR)/flavor_bd/out/%.bit
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car-xil-clean-bd:
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cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_$(XILINX_BOARD) .Xil/
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cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_* .Xil/
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.PHONY: car-xil-clean-bd

‎target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl

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#
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# Cyril Koenig <[email protected]>
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7-
set jtag_gnd_o [ create_bd_port -dir O jtag_gnd_o ]
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set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ]
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set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ]
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set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ]
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set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ]
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set jtag_vdd_o [ create_bd_port -dir O jtag_vdd_o ]
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connect_bd_net -net carfield_xilinx_ip_0_jtag_gnd_o [get_bd_ports jtag_gnd_o] [get_bd_pins carfield_xilinx_ip_0/jtag_gnd_o]
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connect_bd_net -net carfield_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins carfield_xilinx_ip_0/jtag_tdo_o]
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connect_bd_net -net carfield_xilinx_ip_0_jtag_vdd_o [get_bd_ports jtag_vdd_o] [get_bd_pins carfield_xilinx_ip_0/jtag_vdd_o]
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connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tck_i]
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connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tdi_i]
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connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tms_i]

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