From 11c59027e8e814aa0f08657c58c78c3047ebb0b0 Mon Sep 17 00:00:00 2001 From: Colin Roberts Date: Mon, 20 May 2024 12:04:45 -0600 Subject: [PATCH] notes --- src/compiler/mod.rs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/compiler/mod.rs b/src/compiler/mod.rs index d10d37a..36e571f 100644 --- a/src/compiler/mod.rs +++ b/src/compiler/mod.rs @@ -16,6 +16,11 @@ use petgraph::graph::{DiGraph, NodeIndex}; // } // ``` // So we can do things like `impl Add`, `impl Mul` for variables and make them into gates? + +// Above seems done. Now we need to have a way to unravel a collection of expressions into a +// circuit that may have the same inputs and outputs as the expressions. Inputs are going to be +// the terminal variables found by fully unravelling expressions and they should be named. The +// fully ravelled expressions are the outputs, and they can also be named use super::*; pub mod dsl; @@ -58,4 +63,3 @@ pub struct Circuit { impl Circuit { pub fn new() -> Self { Self { gates: DiGraph::new() } } } -