UCF Virtual Workshop 2020

Disclosure

You are registering for an open public standards setting discussion and development meeting of UCF. The discussions that take place during this meeting are intended to be open to the general public and all work product derived therefrom shall be made widely and freely available to the public. All information including exchange of technical information shall take place during open sessions of this meeting and UCF will not sponsor or support any private working group, standards setting or development sessions that may take place during this meeting. Your participation in any non-public interactions or settings during this meeting are outside the scope of UCF's intended open-public meeting format.

Dates

Nov 30 - Dec 3 (4 days)

Free registration for the event

Register here

Location

Virtual - ZOOM (Zoom link to be provided)

Agenda (USA Central time zone)

Date	Time	Topic	Speaker/Moderator
11/30	08:00-09:00	UCF State of the Union Unified Communication Framework (UCF) - Collaboration between industry,laboratories, and academia to create production grade communication frameworks and open standards for data-centric and high-performance applications. In this talk we will present recent advances in development UCF projects including Open UCX, Apache Spark UCX as well incubation projects in the area of SmartNIC programming, benchmarking, and other areas of accelerated compute.	Gilad Shainer, Nvidia Gilad Shainer serves as senior vice-president of marketing for Mellanox networking at NVIDIA, focusing on high- performance computing, artificial intelligence and the InfiniBand technology. Mr. Shainer joined Mellanox in 2001 as a design engineer and later served in senior marketing management roles since 2005. Mr. Shainer serves as the chairman of the HPC-AI Advisory Council organization, the president of UCF and CCIX consortiums, a member of IBTA and a contributor to the PCISIG PCI-X and PCIe specifications. Mr. Shainer holds multiple patents in the field of high-speed networking. He is a recipient of 2015 R&D100 award for his contribution to the CORE-Direct In-Network Computing technology and the 2019 R&D100 award for his contribution to the Unified Communication X (UCX) technology. Gilad Shainer holds a MSc degree and a BSc degree in Electrical Engineering from the Technion Institute of Technology in Israel. Pavel Shamis (Pasha), Arm Pavel Shamis is a Principal Research Engineer at Arm. His work is focused on co-design software, and hardware building blocks for high-performance interconnect technologies, development of communication middleware, and novel programming models. Prior to joining ARM, he spent five years at Oak Ridge National Laboratory (ORNL) as a research scientist at Computer Science and Math Division (CSMD). In this role, Pavel was responsible for research and development multiple projects in high-performance communication domains including Collective Communication Offload (CORE-Direct & Cheetah), OpenSHMEM, and OpenUCX. Before joining ORNL, Pavel spent ten years at Mellanox Technologies, where he led Mellanox HPC team and was one of the key drivers in the enablement Mellanox HPC software stack, including OFA software stack, OpenMPI, MVAPICH, OpenSHMEM, and other. Pavel is a board member of UCF consortium and co-maintainer of Open UCX. He holds multiple patents in the area of in-network accelerator. Pavel is a recipient of 2015 R&D100 award for his contribution to the development CORE-Direct in-network computing technology and the 2019 R&D100 award for the development of Open Unified Communication X (Open UCX) software framework for HPC, data analytics, and AI.
	09:00-10:00	GPU memory support Seamless support of GPU buffers communication introduces yet another dimension for designing optimal data transfer protocols. In this talk we will have open discussion about outstanding issues and challenges, including out-of-box performance, PCI topology support, rendezvous protocols, memory type cache and memory hooks, and more.	Yossi Itigin, Nvidia Yossi Itigin is a UCX team lead at NVIDIA, focuses on high-performance communication middleware, and a maintainer of OpenUCX project. Prior to joining NVIDIA, Mr. Itigin spent nine years at Mellanox Technologies in different technical roles, all related to developing and optimizing RDMA software.
	10:00-11:00	UCX ROCM Plans	Sourav Chandra, AMD
	11:00-11:45	RDMA-CORE: DMA-BUF based GPU RDMA Support The capability of using GPU memory in RDMA operations (a.k.a GPU Direct RDMA) is important for scale-out configuration of GPU computation. In this talk, a dma-buf based approach is presented to enable such capability in the upstream Linux kernel and user space rdma-core libraries.	Jianxin Xiong, Intel Jianxin Xiong works for Intel. His experience covers various layers of interconnection software stack, such as RDMA drivers in Linux kernel, RDMA device virtualization, Open Fabric Interface, DAPL, Tag Matching Interface, and MPI. His current focus is GPU/accelerator scale-out with RDMA devices.
	11:45-12:45	UCX for Apache Spark Utilizing accelerators in Apache Spark presents opportunities for significant speedup of ETL, ML and DL applications. In this talk i’ll describe acceleration of Spark data shuffle across network and GPU accelerators using UCX library. Will show our existing solutions on speeding up host-to-host data transfer, using one-sided communications, device-to-device acceleration for Rapids Spark using tag API, and our roadmap to unify these two solutions.	Peter Rudenko, Nvidia Peter Rudenko is a software engineer in High Performance Computing team, focusing on accelerating data intensive applications, developing UCX communication library and various big data solutions.
	12:45-13:45	UCX Python - Dask/RAPIDS Abstract: Efficient communication is paramount to data science, at the same time being very challenging, given it’s dominated by high-level languages such as Python. We will show how UCX-Py leverages UCX performance greatly for distributed frameworks such as Dask and GPU-accelerated ecosystem RAPIDS. The performance achieved is seen in the COVID-19 research on Summit, the world’s largest supercomputer at ORNL.	Ben Zaitlen, NVIDIA Benjamin Zaitlen is a system software manager for NVIDIA-RAPIDS, focusing on connecting the PyData Ecosystem to accelerated computing and networking Peter Entschev, NVIDIA Peter Entschev is a system software engineer at NVIDIA, working on distributed computing and communications on the RAPIDS team. Matthew Baker, ORNL Matthew graduated from East Tennessee State University (ETSU) with a masters in applied computer science. Matthew’s past work has included working on programming models and high performance network libraries. Matthew’s current work includes monitoring systems at large scale and allowing applications to make decisions at run time.
12/01	08:00-09:00	UCF - Future directions	Steve Poole, Los Alamos National Laboratory
	09:00-10:00	UCP Protocols v2 In order to achieve out-of-box performance, UCX must select the optimal protocol for the given scenario, considering factors such as buffer length, memory locality, and data layout. In this talk we will present and discuss the next version of protocol selection mechanism, and make sure it will be able to handle that task.	Yossi Itigin, Nvidia Yossi Itigin is a UCX team lead at NVIDIA, focuses on high-performance communication middleware, and a maintainer of OpenUCX project. Prior to joining NVIDIA, Mr. Itigin spent nine years at Mellanox Technologies in different technical roles, all related to developing and optimizing RDMA software.
	10:00-11:00	UCP Active messages API Active messages is a common messaging interface for various PGAS (Partitioned Global Address Space) APIs/libraries. In this talk will give an overview of the existing UCP active messaging API, including recently introduced rendezvous protocol capabilities.	Mikhail Brinskii, Nvidia Mikhail Brinskii is a UCX developer with main focus on networking and HPC solutions. Before joining Nvidia, Mikhail had been working at Intel developing highly optimized Intel MPI Library.
	11:00-12:00	UCX development in Huawei Huawei is unique vendor in the HPC landscape, producing all cluster components: Compute (Kunpeng 920 CPU), Storage (OceanStor solutions), Interconnect (RoCE NICs and Switches) and accelerators. This talk will present some of our recent work on UCX – and how it fits in the bigger picture of our HPC solutions.	Alex Margolin, HPC software architect and team leader, Huawei Alex is CS Ph.D. candidate in the area of MPI collective operations, software architect and developer in the areas surrounding MPI performance and low-latency communication. Today, team leader of the cluster computing team in Tel-Aviv Research center, Huawei.
	12:00-13:00	Open Smart NIC API - State of the Union	Steve Poole, Los Alamos National Laboratory
12/02	08:00-09:00	BlazingSQL with UCX	Rodrigo Aramburu & Felipe Aramburu, BlazingSQL
	09:00-10:00	Charm++ with UCX	Nitin Bhat, Charmworks
	10:00-10:30	MPICH/UCX Update	Ken Raffenetti ,Argonne National Laboratory
	10:40-11:40	UCX counters in Score-P and Vampir Score-P is a data acquisition tool which allows collecting profiling and trace data of MPI applications, part of the VI-HPS project. This talk will present (a) a brief introduction to some of the main VI-HPS (Score-P, Cube and Vampir), (b) UCX counters trace data acquisition using Score-P with the Huawei UCX statistics plugin, and (c) Visualization over Vampir.	Shuki Zanyovka, HPC and Networking architect at Huawei An Electrical and SW engineer with background in Statistical Signal Processing, Wireless Communications and Data Science. Past experience: Developing ARM based low-power IoT devices of different types: Cellular Handsets / Digital TV Receivers / Automotive (V2X) and GPON FTTH switches.
	11:40-12:40	Unified Communication Datatypes - State of the Union	Pavan Balaji, Argonne National Laboratory
	12:40-13:00	Arm IP building blocks and standards for SmartNIC This talk describes the building-blocks available from Arm for modern SmartNICs/DPUs along with relevant standards enabling operating systems to boot on Arm-based SmartNICs without modification. Support for interfaces like CXL in Arm IP that targets future SmartNIC architectures is also discussed.	Kshitij Sudan, Arm Kshitij the Technical Assistant to the GM of Arm’s Infrastructure business unit. He is a systems architect and focuses on enabling Arm customers targeted different market segments using Arm IP. Kshitij holds a PhD in computer architecture from University of Utah.
12/03	08:00-09:00	UCC: Design and Implementation of Next Generation Collectives Library UCC is a community-driven effort to develop collective API and library implementation for applications in various domains, including High-Performance Computing, Artificial Intelligence, Data Center, and I/O. Over the last few months, the UCC WG group has met weekly to develop the UCC specification. In this talk, I will highlight some of the design principles of the UCC v1.0 specification. I will also share the status of UCC implementation and upcoming plans of the working group. Further, we will share results from the experimental implementation - XCCL, which has helped make an informed decision regarding UCC interfaces and semantics.	Manjunath Gorentla Venkata, Nvidia Manjunath Gorentla Venkata is an HPC software architect at NVIDIA. His focus is on programming models and network libraries for HPC systems. Previously, he was a research scientist and the Languages Team lead at Oak Ridge National Laboratory. He's served on open standards committees for parallel programming models, including OpenSHMEM and MPI for many years, and he is the author of more than 50 research papers in this area. Manju earned Ph.D. and M.S. degrees in computer science from the University of New Mexico.
	09:00-09:30	One-to-many UCT transports, part I: Shared-memory Though UCX stands for unified communication, the focus has been on P2P. This talk presents the first part of our work on broadcast communication – inter-process communication within the same host. This new UCT transport significantly accelerates MPI’s Barrier, Bcast, Reduce, Allreduce, Scatter and Gather.	Alex Margolin, HPC software architect and team leader, Huawei Alex is CS Ph.D. candidate in the area of MPI collective operations, software architect and developer in the areas surrounding MPI performance and low-latency communication. Today, team leader of the cluster computing team in Tel-Aviv Research center, Huawei.
	09:30-10:00	One-to-many UCT transports, part II: Multicast Though UCX stands for unified communication, the focus has been on P2P. This talk presents the first part of our work on broadcast communication – inter-process communication within the same host. This new UCT transport significantly accelerates MPI’s Barrier, Bcast, Reduce, Allreduce, Scatter and Gather.	Morad Horany, HPC software developer, Huawei Computer Engineering Bs.C., previously a Firmware Engineer for NICs at Mellanox in the areas of Quality of Service and Virtualization, now member of the cluster computing team in Tel-Aviv Research center, Huawei.
	10:00-11:00	Until UCC is available - UCG status update A lot has happened since UCG’s 1st pull-request, back in 2018: the API has matured, optimizations across UCX have been implemented (some accepted upstream) by team members in China and in Israel, and this talk will present the journey so far – and the road ahead.	Alex Margolin, HPC software architect and team leader, Huawei Alex is CS Ph.D. candidate in the area of MPI collective operations, software architect and developer in the areas surrounding MPI performance and low-latency communication. Today, team leader of the cluster computing team in Tel-Aviv Research center, Huawei.
	11:00-11:45	RDMA-CORE Linux kernel and user space updates	Jason Gunthorpe, Nvidia
	11:45-12:45	Scaling Facebook's Deep Learning Recommender Model (DLRM) with UCC/XCCL	Josh Ladd, Nvidia & Srinivas, Facebook
	12:45-13:30	Open Smart NIC API - OpenSHMEM I/O Extensions for Fine-grained Access to Persistent Memory Storage	Megan Grodowitz, Arm