[BUG] SBE/UBE/MBE Bit in mstatus Register Does Not Affect Endianness of Explicit Memory Accesses

[riscv914]

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

According to the RISC-V ISA specification, the MBE, SBE, and UBE bits in the mstatus and mstatush registers control the endianness of memory accesses, except for instruction fetches, which are always little-endian. Specifically:

• MBE controls whether memory accesses from M-mode are little-endian (MBE=0) or big-endian (MBE=1).
• SBE controls the endianness for memory accesses in S-mode, provided S-mode is supported.
• UBE controls the endianness for memory accesses in U-mode, provided U-mode is supported.
• The SBE field is essential for controlling endianness in supervisor-level memory management operations like page table accesses. If the SBE bit changes, M-mode software is required to execute the SFENCE.VMA instruction to ensure consistency in accessing supervisor-level structures.

However, on the CVA6 core, setting the MBE bit in mstatus does not affect the expected behavior of explicit load and store operations. Specifically, even when the MBE bit is manipulated (by clearing or setting it), the endianness of the subsequent sw (store word) and lb (load byte) instructions is not affected as expected.

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Code for Reproducing the Bug:

asm volatile ("csrr t0, mstatus");
asm volatile ("li t0, 0x2000000000"); // Clear MBE (bit 37)
asm volatile ("csrc mstatus, t0");
asm volatile ("csrr t0, mstatus");
asm volatile ("li t0, 0x12345678");
asm volatile ("li t1, 0x81000000");
asm volatile ("sw t0, 0(t1)");
asm volatile ("lb t0, 0(t1)");

asm volatile ("li t0, 0x2000000000"); // Set MBE (bit 37)
asm volatile ("csrs mstatus, t0");
asm volatile ("csrr t0, mstatus");
asm volatile ("li t0, 0x12345678");
asm volatile ("li t1, 0x81000000");
asm volatile ("sw t0, 0(t1)");
asm volatile ("lb t0, 0(t1)");
asm volatile ("addi t0,t0,0");

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Expected Behavior:

When the MBE bit in mstatus is cleared or set, the endianness of memory accesses (explicit loads and stores) should change accordingly. Specifically, the sw (store word) and lb (load byte) instructions should behave as expected with the appropriate endianness (little-endian when MBE=0, big-endian when MBE=1).

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Observed Behavior:

When manipulating the MBE bit in mstatus, the endianness of memory accesses is not affected, and the behavior of sw and lb instructions does not change as expected.

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CVA6 commit: 2155d0e
Build config: cv64a6_imafdch_sv39_wb

[JeanRochCoulon]

https://docs.openhwgroup.org/projects/cva6-user-manual/04_cv32a65x/riscv/priv.html#_endianness_control_in_mstatus_and_mstatush_registers explains that MBE is read only zero. This is the case for 65x and other configurations. This implies that cva6 is always little-endian. I am quite surprise of this issue could be set to one because CSR right access should have been verified. @AyoubJalali what do you think ?
@ASintzoff

[ASintzoff]

As MBE belongs to the high part of mstatus on RV64 and to mstatush on RV32, the behaviour could be different. As mstatush is read-only 0 on RV32 CVA6 configurations, the issue raised by @riscv914 was not identified.

On RV64 CVA6 configurations, it appears that MBE bit can be modified even it should not.

[AyoubJalali]

As I know for the CV32A65X the MBE is read-only zero.