[BUG] interrupts delegattion Not Masked in M-Mode as Expected

[riscv914]

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

According to the RISC-V ISA, delegated interrupts should result in the interrupt being masked at the delegator privilege level. For example, if the Supervisor Timer Interrupt (STI) is delegated to S-mode by setting mideleg[5], STIs should not be taken when executing in M-mode. If mideleg[5] is cleared, STIs can be taken in any mode, and regardless of the current mode, control should transfer to M-mode.

However, when the STI interrupt is delegated to S-mode and the interrupt is triggered, the interrupt is not masked in M-mode as expected. It remains visible in M-mode even though it should be masked, and we can see the interrupt in the mip register.

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Code for Reproducing the Bug:

int main() {
    asm volatile ("li t0, 0x20"); 
    asm volatile ("csrs mip, t0");  // Set STI interrupt in mip
    asm volatile ("csrr t0, mip");  // Read the mip register (Check mask)
    asm volatile ("csrr t0, sip");  // Read the sip register (shows delegation)
}

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Expected Behavior:

When the STI interrupt is delegated to S-mode, and the interrupt is triggered, it should be masked in M-mode and should not be visible in the mip register while executing in M-mode. The interrupt should be visible in the sip register when executing in S-mode.

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Observed Behavior:

The STI interrupt is still visible in M-mode, even though it should be masked due to the delegation to S-mode. This violates the expected behavior as defined by the RISC-V ISA for delegated interrupts.

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CVA6 commit: 2155d0e
Build config : cv64a6_imafdch_sv39_wb

[JeanRochCoulon]

Great finding. As S mode is not supported for 65x and 60x, I add the notCV32A65X label.