[BUG] PMP CSR : NAPOT MODE isn't supported

[AyoubJalali]

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

Hello, according to the cv32a65x, in the pmp entries the NA4 & NAPOT modes isn't supported, but in the RTL is only excluding NA4 from the add_mode logic in csr_regfile.sv

is it a bug in the RTL or the Specification ?

[AyoubJalali]

I think this is a RTL bug

[zchamski]

Results of a careful review of the spec and RTL with @ASintzoff:

• the spec of CV32A65X does not specify the actual WARL behavior upon writing an invalid (illegal/reserved) multi-bit value for RWX and A fields; this is required given the definition of WARL at https://cva6.readthedocs.io/en/latest/04_cv32a65x/riscv/priv.html#_write_any_values_reads_legal_values_warl;
• the RTL implements 'no change on reserved' policy for the aggregate RWX field;
• the RTL implements 'no change on illegal' policy for A fields but does allow A == NAPOT which conflicts with the CV32A65X spec supporting only A == OFF and A == TOR.

The RTL needs to be fixed for CV32A65X but without affecting other configurations.