xe: jit: enable nGEN debug information

rjoursler · rjoursler · commit cac7865fe09b · 2025-01-02T13:03:52.000-08:00
diff --git a/src/gpu/intel/jit/binary_format.cpp b/src/gpu/intel/jit/binary_format.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2019-2024 Intel Corporation
+* Copyright 2019-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -52,7 +52,8 @@ class binary_format_kernel_t : public jit_generator<hw> {
     NGEN_FORWARD_OPENCL(hw);
 
 public:
-    binary_format_kernel_t() {
+    binary_format_kernel_t()
+        : jit_generator<hw>({GENERATOR_NAME, GENERATOR_LINE}) {
 
         auto low_half = [](uint64_t q) -> uint32_t { return q & 0xFFFFFFFF; };
         auto high_half = [](uint64_t q) -> uint32_t { return q >> 32; };
diff --git a/src/gpu/intel/jit/codegen/kernel.hpp b/src/gpu/intel/jit/codegen/kernel.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2022-2024 Intel Corporation
+* Copyright 2022-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -187,9 +187,11 @@ class ir_kernel_t : public jit_generator<hw> {
     friend class ir_to_ngen_t<hw>;
     friend class send_impl_t;
 
-    ir_kernel_t(
-            const kernel_desc_base_t &desc, const kernel_info_t &kernel_info)
-        : kernel_name_(desc.kernel_name())
+    ir_kernel_t(const kernel_desc_base_t &desc,
+            const kernel_info_t &kernel_info,
+            const debug_config_t &debug_config)
+        : jit_generator<hw>(debug_config)
+        , kernel_name_(desc.kernel_name())
         , exec_cfg_(desc.exec_cfg())
         , kernel_info_(kernel_info)
         , local_range_(desc.local_range())
@@ -203,8 +205,10 @@ class ir_kernel_t : public jit_generator<hw> {
 
     ir_kernel_t(const std::string &kernel_name, const exec_config_t &exec_cfg,
             const kernel_info_t &kernel_info,
-            const compute::range_t &local_range, bool require_dpas)
-        : kernel_name_(kernel_name)
+            const compute::range_t &local_range, bool require_dpas,
+            const debug_config_t &debug_config)
+        : jit_generator<hw>(debug_config)
+        , kernel_name_(kernel_name)
         , exec_cfg_(exec_cfg)
         , kernel_info_(kernel_info)
         , local_range_(local_range)
diff --git a/src/gpu/intel/jit/conv/conv_kernel.hpp b/src/gpu/intel/jit/conv/conv_kernel.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2021-2024 Intel Corporation
+* Copyright 2021-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -56,7 +56,8 @@ conv_kernel_t<hw>::conv_kernel_t(const conv_config_t &cfg,
         const kernel_info_t &kernel_info, const compute::range_t &local_range,
         const layout_t &zp_dst)
     : ir_kernel_t<hw>("gen_conv", cfg.exec_cfg(), kernel_info, local_range,
-            utils::one_of(cfg.fma_kind(), fma_kind_t::dpas, fma_kind_t::dpasw))
+            utils::one_of(cfg.fma_kind(), fma_kind_t::dpas, fma_kind_t::dpasw),
+            {GENERATOR_NAME, GENERATOR_LINE})
     , prb_(cfg.prb())
     , cfg_(cfg) {
 
diff --git a/src/gpu/intel/jit/conv/zero_out.hpp b/src/gpu/intel/jit/conv/zero_out.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2022-2024 Intel Corporation
+* Copyright 2022-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -36,7 +36,8 @@ class zero_out_kernel_t : public ir_kernel_t<hw> {
     zero_out_kernel_t(const exec_config_t &exec_cfg,
             const kernel_info_t &kernel_info, bool require_dpas)
         : ir_kernel_t<hw>("zero_out", exec_cfg, kernel_info,
-                kernel_info.nd_range().local_range(), require_dpas) {
+                kernel_info.nd_range().local_range(), require_dpas,
+                {GENERATOR_NAME, GENERATOR_LINE}) {
 
         setup_interface();
         generate_prologue();
diff --git a/src/gpu/intel/jit/emulated_generator.hpp b/src/gpu/intel/jit/emulated_generator.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright 2024 Intel Corporation
+ * Copyright 2024-2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -40,9 +40,11 @@ class emulated_generator_t : public jit_generator<hw> {
     NGEN_FORWARD_OPENCL(hw);
 
 public:
-    emulated_generator_t(
-            const compute::device_info_t &device_info, const std::string &name)
-        : ra_(hw, name), emu_strategy(hw, device_info.stepping_id()) {}
+    emulated_generator_t(const compute::device_info_t &device_info,
+            const std::string &name, const debug_config_t &debug_config)
+        : jit_generator<hw>(debug_config)
+        , ra_(hw, name)
+        , emu_strategy(hw, device_info.stepping_id()) {}
 
 protected:
     reg_allocator_t ra_;
diff --git a/src/gpu/intel/jit/gemm/include/generator.hpp b/src/gpu/intel/jit/gemm/include/generator.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2019-2024 Intel Corporation
+* Copyright 2019-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -65,7 +65,7 @@ class BLASKernelGenerator : public GENERATOR_BASE(hw) {
 public:
     using super = GENERATOR_SUPER(hw);
 
-    BLASKernelGenerator() {}
+    BLASKernelGenerator(): GENERATOR_BASE(hw)({GENERATOR_NAME, GENERATOR_LINE}) {}
 
     FORWARD(hw)
 
diff --git a/src/gpu/intel/jit/gen9_simple_sum_kernel_f32.hpp b/src/gpu/intel/jit/gen9_simple_sum_kernel_f32.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright 2019-2024 Intel Corporation
+ * Copyright 2019-2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -29,7 +29,8 @@ namespace jit {
 
 class gen9_simple_sum_kernel_f32_t : public jit_generator<gpu_gen9> {
 public:
-    gen9_simple_sum_kernel_f32_t() : jit_generator<gpu_gen9>() {
+    gen9_simple_sum_kernel_f32_t()
+        : jit_generator<gpu_gen9>({GENERATOR_NAME, GENERATOR_LINE}) {
         using namespace ngen;
         constexpr auto GlobalPtr = ExternalArgumentType::GlobalPtr;
         constexpr auto Scalar = ExternalArgumentType::Scalar;
diff --git a/src/gpu/intel/jit/jit_generator.hpp b/src/gpu/intel/jit/jit_generator.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2019-2024 Intel Corporation
+* Copyright 2019-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -111,6 +111,19 @@ struct jit_reduction_injector_f32;
 template <gpu_gen_t hw>
 struct jit_post_op_injector;
 
+#if (!defined(NDEBUG) || defined(DNNL_DEV_MODE))
+#define GENERATOR_NAME __FILE__
+#define GENERATOR_LINE __LINE__
+#else
+#define GENERATOR_NAME "oneDNN"
+#define GENERATOR_LINE 0
+#endif
+
+struct debug_config_t {
+    const char *name;
+    uint32_t line;
+};
+
 template <gpu_gen_t hw>
 class jit_generator : public ngen::OpenCLCodeGenerator<hw>,
                       public jit_generator_base {
@@ -130,9 +143,15 @@ class jit_generator : public ngen::OpenCLCodeGenerator<hw>,
     };
     std::unique_ptr<void, svm_deleter> dbg_memory_;
 #endif
-
+#ifdef DNNL_DEV_MODE
+    static constexpr bool enable_debug_lines = true;
+#else
+    static constexpr bool enable_debug_lines = false;
+#endif
 public:
-    jit_generator() = default;
+    jit_generator(const debug_config_t &debug_config)
+        : ngen::OpenCLCodeGenerator<hw>(0,
+                {debug_config.name, debug_config.line, enable_debug_lines}) {};
 
     const char *kernel_name() const override {
         return ngen::OpenCLCodeGenerator<hw>::getExternalName().c_str();
diff --git a/src/gpu/intel/jit/jit_reduction_generator.hpp b/src/gpu/intel/jit/jit_reduction_generator.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright 2024 Intel Corporation
+ * Copyright 2024-2025 Intel Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -43,7 +43,8 @@ class jit_reduction_generator_t : public emulated_generator_t<hw> {
 public:
     jit_reduction_generator_t(const compute::device_info_t &device_info,
             alg_kind_t alg, dim_t stride, dim_t iters, int nregs)
-        : emulated_generator_t<hw>(device_info, "ngen_jit_reduction") {
+        : emulated_generator_t<hw>(device_info, "ngen_jit_reduction",
+                {GENERATOR_NAME, GENERATOR_LINE}) {
         constexpr auto GlobalPtr = ngen::ExternalArgumentType::GlobalPtr;
 
         // Number of dst elements computed per thread
diff --git a/src/gpu/intel/jit/ngen/ngen_config.hpp b/src/gpu/intel/jit/ngen/ngen_config.hpp
@@ -31,4 +31,13 @@ using half = dnnl::impl::float16_t;
 #define NGEN_BFLOAT16_TYPE
 #define NGEN_HALF_TYPE
 
+#if (!defined(NDEBUG) || defined(DNNL_DEV_MODE)) && (__cplusplus >= 202002L || _MSVC_LANG >= 202002L)
+#if __has_include(<version>)
+#include <version>
+#if __cpp_lib_source_location >= 201907L
+#define NGEN_ENABLE_SOURCE_LOCATION true
+#endif
+#endif
+#endif
+
 #endif /* header guard */
diff --git a/src/gpu/intel/jit/pooling/pooling_kernel.hpp b/src/gpu/intel/jit/pooling/pooling_kernel.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2023-2024 Intel Corporation
+* Copyright 2023-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -41,7 +41,8 @@ class pooling_kernel_t : public ir_kernel_t<hw> {
     pooling_kernel_t(pooling_config_t &cfg, const std::string &kernel_name,
             const kernel_info_t &kernel_info, const primitive_desc_t &pd)
         : ir_kernel_t<hw>(kernel_name, cfg.exec_cfg(), kernel_info,
-                kernel_info.nd_range().local_range(), /*require_dpas=*/false) {
+                kernel_info.nd_range().local_range(), /*require_dpas=*/false,
+                {GENERATOR_NAME, GENERATOR_LINE}) {
         pooling_ir_builder_t builder(cfg, kernel_info, pd);
         stmt_t body = builder.stmt();
         setup_interface(body);
diff --git a/src/gpu/intel/jit/reorder/reorder_kernel.hpp b/src/gpu/intel/jit/reorder/reorder_kernel.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2022-2024 Intel Corporation
+* Copyright 2022-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -43,7 +43,8 @@ class reorder_kernel_t : public ir_kernel_t<hw> {
             const std::string &kernel_name, const kernel_info_t &kernel_info,
             bool require_dpas, const primitive_desc_t *pd = nullptr)
         : ir_kernel_t<hw>(kernel_name, cfg.exec_cfg(), kernel_info,
-                kernel_info.nd_range().local_range(), require_dpas) {
+                kernel_info.nd_range().local_range(), require_dpas,
+                {GENERATOR_NAME, GENERATOR_LINE}) {
         const primitive_attr_t *attr = (pd) ? pd->attr() : nullptr;
         const memory_desc_t *dst_md = (pd) ? pd->dst_md() : nullptr;
         reorder_ir_builder_t builder(cfg, kernel_info, attr, dst_md);
diff --git a/src/gpu/intel/jit/v2/conv/kernel.hpp b/src/gpu/intel/jit/v2/conv/kernel.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
-* Copyright 2023-2024 Intel Corporation
+* Copyright 2023-2025 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
@@ -45,7 +45,7 @@ class kernel_t : public ir_kernel_t<hw> {
 template <ngen::HW hw>
 kernel_t<hw>::kernel_t(
         const kernel_desc_base_t &_desc, const kernel_info_t &kernel_info)
-    : ir_kernel_t<hw>(_desc, kernel_info) {
+    : ir_kernel_t<hw>(_desc, kernel_info, {GENERATOR_NAME, GENERATOR_LINE}) {
 
     auto &desc = static_cast<const kernel_desc_t &>(_desc);
 
