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test_targets: capture output ci #29: Commit a264f59 pushed by AndrewD
October 20, 2023 01:09 41m 51s test_targets
test_targets
October 20, 2023 01:09 41m 51s
test_targets: adjust to enumerate litex_boards mobdule ci #28: Commit 24a3531 pushed by AndrewD
October 20, 2023 00:48 42m 2s test_targets
test_targets
October 20, 2023 00:48 42m 2s
build/openocd: adding Efinix Titanium support ci #27: Commit 7e64189 pushed by AndrewD
October 20, 2023 00:28 36m 3s master
master
October 20, 2023 00:28 36m 3s
soc_core: support legacy integrated_main_ram_size test ci #26: Commit 3d0e2bd pushed by AndrewD
October 20, 2023 00:04 35m 47s parser_soc_args_fix
parser_soc_args_fix
October 20, 2023 00:04 35m 47s
parser: set default soc ident to description ci #25: Commit 7d39651 pushed by AndrewD
October 20, 2023 00:04 36m 40s parser_soc_args
parser_soc_args
October 20, 2023 00:04 36m 40s
test_targets: don't exclude based on toolchain ci #24: Commit 62dbc7c pushed by AndrewD
October 20, 2023 00:01 36m 26s test_targets
test_targets
October 20, 2023 00:01 36m 26s
soc/add_ethernet: add optional etherbone ci #23: Commit bf4a451 pushed by AndrewD
October 16, 2023 06:37 33m 9s etherbone
etherbone
October 16, 2023 06:37 33m 9s
build/openfpgaloader: Add unprotect_flash capability. ci #22: Commit e499dd8 pushed by AndrewD
October 16, 2023 06:14 58m 43s master
master
October 16, 2023 06:14 58m 43s
parser: set default soc ident to description ci #21: Commit db932b0 pushed by AndrewD
October 16, 2023 05:54 33m 3s sim_verilog_only
sim_verilog_only
October 16, 2023 05:54 33m 3s
soc_core: default add_args() ci #20: Commit aee463d pushed by AndrewD
October 16, 2023 05:35 45m 6s sim_verilog_only
sim_verilog_only
October 16, 2023 05:35 45m 6s
soc/add_ethernet: add optional etherbone ci #19: Commit 7fe9716 pushed by AndrewD
October 16, 2023 05:35 58m 21s etherbone
etherbone
October 16, 2023 05:35 58m 21s
build/sim: specify language for verilog-only sources ci #18: Commit 5e9ff8e pushed by AndrewD
October 14, 2023 23:27 36m 42s sim_verilog_only
sim_verilog_only
October 14, 2023 23:27 36m 42s
soc_core: support legacy ident=None ci #17: Commit 505645a pushed by AndrewD
October 13, 2023 11:13 3h 34m 37s sim_verilog_only
sim_verilog_only
October 13, 2023 11:13 3h 34m 37s
build/sim: specify language for verilog-only sources ci #16: Commit 946d3d3 pushed by AndrewD
October 13, 2023 07:05 33m 3s sim_verilog_only
sim_verilog_only
October 13, 2023 07:05 33m 3s
build/sim: specify language for verilog-only sources ci #15: Commit f017a28 pushed by AndrewD
October 13, 2023 06:54 34m 2s sim_verilog_only
sim_verilog_only
October 13, 2023 06:54 34m 2s
litex_json2renode: fix --bios-binary and add --opensbi-binary ci #14: Commit 564f96c pushed by AndrewD
September 25, 2023 09:35 34m 41s json2renode
json2renode
September 25, 2023 09:35 34m 41s
litex_json2renode: fix --bios-binary and add --opensbi-binary ci #13: Commit 2853942 pushed by AndrewD
September 23, 2023 08:44 1h 21m 15s json2renode
json2renode
September 23, 2023 08:44 1h 21m 15s
vexrisc_smp: fix DMA bus address_width calculation ci #12: Commit 1bb4d29 pushed by AndrewD
September 2, 2023 01:46 29m 56s dma_fix
dma_fix
September 2, 2023 01:46 29m 56s
tools/litex_json2dts_linux: fix missed sdcard_ references ci #11: Commit 058cdd6 pushed by AndrewD
September 1, 2023 06:55 30m 1s dts_linux_fix
dts_linux_fix
September 1, 2023 06:55 30m 1s
Merge pull request #1758 from motec-research/spi_mmap_fix ci #10: Commit 1401226 pushed by AndrewD
September 1, 2023 06:48 31m 37s master
master
September 1, 2023 06:48 31m 37s
build/parser: change to BooleanOptionalAction ci #9: Commit d2c612b pushed by AndrewD
September 1, 2023 03:08 55m 41s builder_enhancements
builder_enhancements
September 1, 2023 03:08 55m 41s
soc/cores/spi_mmap: Fix clock divider ci #8: Commit d494e30 pushed by AndrewD
September 1, 2023 03:08 55m 48s spi_mmap_fix
spi_mmap_fix
September 1, 2023 03:08 55m 48s
interconnect/axi/axi_full: Fix missing switch to LiteXModule. ci #7: Commit 405296b pushed by AndrewD
September 1, 2023 02:32 55m 36s master
master
September 1, 2023 02:32 55m 36s
litex/gen/sim: add Tristate special override ci #6: Commit 8dbdeb0 pushed by AndrewD
September 1, 2023 02:32 55m 45s sim_tristate
sim_tristate
September 1, 2023 02:32 55m 45s