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Optimize FPGAs #644
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This is a good idea as long as FPGAs remain as they are, i.e. without the possibility of back-referencing registers in order to create flipflops, which is a change I wanted to propose, because I implemented it for building a computer in minetest by just using logic gates and FPGAs, and it turned out to work well: |
A mesecon FPGA performs computation on each input change, which takes CPU time. But, it has only 4-bit input, which is just 16 possible states. Thus its output can be precomputed and stored in the metadata as a 16-byte string (technically only 64 bits are needed but packing into a 8-byte string would be too cumbersome).
Previous attempt: #631.
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