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[SPI, dv] Missing SPI pass through test with two stages read pipeline #24597

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sha-ron opened this issue Sep 18, 2024 · 0 comments

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Earlgrey-PROD.M7

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sha-ron commented Sep 18, 2024

Description

SPI top level test (not unit level) that can run on VCS simulation and configures CMD_INFO.read_pipeline_mode to 0x2.
https://opentitan.org/book/hw/ip/spi_device/doc/registers.html#cmd_info--read_pipeline_mode

sha-ron added this to the Earlgrey-PROD.M7 milestone

sha-ron mentioned this issue

[SPI,dv] Remove 30MHz SCK usage when not using two_stages_full_cycle … #24601

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