From bc11a5dde0b576c33593f30aa36b5d36ecfca9eb Mon Sep 17 00:00:00 2001 From: guochen2 Date: Thu, 9 Jan 2025 13:39:37 -0500 Subject: [PATCH] VOPC true16 --- .../Disassembler/AMDGPUDisassembler.cpp | 19 +- .../AMDGPU/Disassembler/AMDGPUDisassembler.h | 1 + llvm/lib/Target/AMDGPU/VOPCInstructions.td | 190 ++++++++++----- llvm/lib/Target/AMDGPU/VOPInstructions.td | 2 +- .../AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s | 123 +++++----- .../MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s | 55 +++-- .../test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s | 36 ++- llvm/test/MC/AMDGPU/gfx11_asm_vopc.s | 160 ++++++++----- llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s | 216 +++++++++++++----- llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s | 48 +++- llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s | 150 ++++++++---- .../MC/AMDGPU/gfx11_asm_vopc_t16_promote.s | 154 +++++++++---- llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s | 40 +++- llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s | 139 ++++++----- llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s | 71 +++--- llvm/test/MC/AMDGPU/gfx12_asm_vopc.s | 152 +++++++----- llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s | 208 ++++++++++++----- llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s | 40 +++- llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s | 150 ++++++++---- .../MC/AMDGPU/gfx12_asm_vopc_t16_promote.s | 196 +++++++++++----- .../gfx11_dasm_vop3_dpp16_from_vopc.txt | 103 ++++++--- .../AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt | 49 ++-- .../AMDGPU/gfx11_dasm_vop3_from_vopc.txt | 32 ++- .../Disassembler/AMDGPU/gfx11_dasm_vopc.txt | 148 +++++++++--- .../AMDGPU/gfx11_dasm_vopc_dpp16.txt | 110 ++++++--- .../AMDGPU/gfx11_dasm_vopc_dpp8.txt | 38 ++- .../Disassembler/AMDGPU/gfx12_dasm_vop3c.txt | 33 ++- .../AMDGPU/gfx12_dasm_vop3c_dpp16.txt | 109 ++++++--- .../AMDGPU/gfx12_dasm_vop3c_dpp8.txt | 55 +++-- .../Disassembler/AMDGPU/gfx12_dasm_vopc.txt | 122 +++++++--- .../AMDGPU/gfx12_dasm_vopc_dpp16.txt | 104 ++++++--- .../AMDGPU/gfx12_dasm_vopc_dpp8.txt | 33 ++- 32 files changed, 2146 insertions(+), 940 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index d2363274965a3..31f47b6125bd7 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -668,9 +668,10 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) convertVOP3PDPPInst(MI); - else if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) || - AMDGPU::isVOPC64DPP(MI.getOpcode())) + else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) convertVOPCDPPInst(MI); // Special VOP3 case + else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) + convertVOPC64DPPInst(MI); // Special VOP3 case else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) != -1) convertDPP8Inst(MI); @@ -1254,6 +1255,20 @@ void AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { AMDGPU::OpName::src1_modifiers); } +void AMDGPUDisassembler::convertVOPC64DPPInst(MCInst &MI) const { + unsigned Opc = MI.getOpcode(); + unsigned DescNumOps = MCII->get(Opc).getNumOperands(); + + convertTrue16OpSel(MI); + + if (MI.getNumOperands() < DescNumOps && + AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { + auto Mods = collectVOPModifiers(MI); + insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), + AMDGPU::OpName::op_sel); + } +} + void AMDGPUDisassembler::convertFMAanyK(MCInst &MI, int ImmLitIdx) const { assert(HasLiteral && "Should have decoded a literal"); const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h index 9a06cc3dc8c78..29452166e21a0 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -210,6 +210,7 @@ class AMDGPUDisassembler : public MCDisassembler { void convertVOP3DPPInst(MCInst &MI) const; void convertVOP3PDPPInst(MCInst &MI) const; void convertVOPCDPPInst(MCInst &MI) const; + void convertVOPC64DPPInst(MCInst &MI) const; void convertMacDPPInst(MCInst &MI) const; void convertTrue16OpSel(MCInst &MI) const; diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td index 8589d598f5870..1c4c572ad0308 100644 --- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td @@ -89,23 +89,57 @@ multiclass VOPC_Profile_t16 sched, ValueType vt0, ValueType def _t16 : VOPC_Profile { let IsTrue16 = 1; let IsRealTrue16 = 1; - let Src1RC32 = getVregSrcForVT.ret; - let Src0DPP = getVregSrcForVT.ret; - let Src1DPP = getVregSrcForVT.ret; - let Src2DPP = getVregSrcForVT.ret; - let Src0ModDPP = getSrcModDPP_t16.ret; - let Src1ModDPP = getSrcModDPP_t16.ret; - let Src2ModDPP = getSrcModDPP_t16.ret; + let HasOpSel = 1; + let HasModifiers = 1; // All instructions at least have OpSel + let DstRC = getVALUDstForVT.ret; + let Src0RC32 = getVOPSrc0ForVT.ret; + let Src1RC32 = getVregSrcForVT.ret; + let Src0DPP = getVregSrcForVT.ret; + let Src1DPP = getVregSrcForVT.ret; + let Src2DPP = getVregSrcForVT.ret; + let Src0ModDPP = getSrcModDPP_t16.ret; + let Src1ModDPP = getSrcModDPP_t16.ret; + let Src2ModDPP = getSrcModDPP_t16.ret; + let Src0VOP3DPP = VGPRSrc_16; + let Src1VOP3DPP = getVOP3DPPSrcForVT.ret; + let Src2VOP3DPP = getVOP3DPPSrcForVT.ret; + + let DstRC64 = getVALUDstForVT.ret; + let Src0RC64 = getVOP3SrcForVT.ret; + let Src1RC64 = getVOP3SrcForVT.ret; + let Src2RC64 = getVOP3SrcForVT.ret; + let Src0Mod = getSrc0Mod.ret; + let Src1Mod = getSrcMod.ret; + let Src2Mod = getSrcMod.ret; + let Src0ModVOP3DPP = getSrc0ModVOP3DPP.ret; + let Src1ModVOP3DPP = getSrcModVOP3DPP.ret; + let Src2ModVOP3DPP = getSrcModVOP3DPP.ret; } def _fake16: VOPC_Profile { let IsTrue16 = 1; + let DstRC = getVALUDstForVT_fake16.ret; + let Src0RC32 = getVOPSrc0ForVT.ret; let Src1RC32 = getVregSrcForVT.ret; let Src0DPP = getVregSrcForVT.ret; let Src1DPP = getVregSrcForVT.ret; let Src2DPP = getVregSrcForVT.ret; - let Src0ModDPP = getSrcModDPP_t16.ret; - let Src1ModDPP = getSrcModDPP_t16.ret; - let Src2ModDPP = getSrcModDPP_t16.ret; + let Src0ModDPP = getSrcModDPP_t16.ret; + let Src1ModDPP = getSrcModDPP_t16.ret; + let Src2ModDPP = getSrcModDPP_t16.ret; + let Src0VOP3DPP = VGPRSrc_32; + let Src1VOP3DPP = getVOP3DPPSrcForVT.ret; + let Src2VOP3DPP = getVOP3DPPSrcForVT.ret; + + let DstRC64 = getVALUDstForVT.ret; + let Src0RC64 = getVOP3SrcForVT.ret; + let Src1RC64 = getVOP3SrcForVT.ret; + let Src2RC64 = getVOP3SrcForVT.ret; + let Src0Mod = getSrc0Mod.ret; + let Src1Mod = getSrcMod.ret; + let Src2Mod = getSrcMod.ret; + let Src0ModVOP3DPP = getSrc0ModVOP3DPP.ret; + let Src1ModVOP3DPP = getSrcModVOP3DPP.ret; + let Src2ModVOP3DPP = getSrcModVOP3DPP.ret; } } @@ -283,7 +317,9 @@ class getVOPCPat64 : LetDummies { (setcc (P.Src0VT !if(P.HasOMod, (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), - (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))), + !if(P.HasClamp, + (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp), + (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers)))), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), cond))], [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]); @@ -324,6 +360,10 @@ multiclass VOPC_Pseudos op, VOPC_Pseudo ps, string opName = ps.OpName> // VOPC64 -class VOPC64_DPP_Base op, string OpName, VOPProfile P> - : VOP3_DPP_Base, VOP3_DPPe_Common { +class VOPC64_DPP + : VOP3_DPP_Base { Instruction Opcode = !cast(NAME); - - bits<8> src0; - bits<9> dpp_ctrl; - bits<1> bound_ctrl; - bits<4> bank_mask; - bits<4> row_mask; - bit fi; - - let Inst{40-32} = 0xfa; - let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); - let Inst{80-72} = dpp_ctrl; - let Inst{82} = fi; - let Inst{83} = bound_ctrl; - // Inst{87-84} ignored by hw - let Inst{91-88} = bank_mask; - let Inst{95-92} = row_mask; -} - -class VOPC64_DPP16 op, VOP_DPP_Pseudo ps, string opName = ps.OpName> - : VOPC64_DPP_Base { let AssemblerPredicate = HasDPP16; let SubtargetPredicate = HasDPP16; let True16Predicate = ps.True16Predicate; @@ -1380,32 +1400,35 @@ class VOPC64_DPP16 op, VOP_DPP_Pseudo ps, string opName = ps.OpName> class VOPC64_DPP16_Dst op, VOP_DPP_Pseudo ps, string opName = ps.OpName> - : VOPC64_DPP16 { + : VOPC64_DPP, VOP3_DPP_Enc { bits<8> sdst; let Inst{7-0} = sdst; } class VOPC64_DPP16_NoDst op, VOP_DPP_Pseudo ps, string opName = ps.OpName> - : VOPC64_DPP16 { + : VOPC64_DPP, VOP3_DPP_Enc { let Inst{7-0} = ? ; } -class VOPC64_DPP8_Base op, string OpName, VOPProfile P> - : VOP3_DPP8_Base, VOP3_DPPe_Common { - Instruction Opcode = !cast(NAME); - - bits<8> src0; - bits<24> dpp8; - bits<9> fi; +class VOPC64_DPP16_Dst_t16 op, VOP_DPP_Pseudo ps, + string opName = ps.OpName> + : VOPC64_DPP, VOP3_DPP_Enc_t16 { + bits<8> sdst; + let Inst{7-0} = sdst; + let Inst{14} = 0; +} - let Inst{40-32} = fi; - let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); - let Inst{95-72} = dpp8{23-0}; +class VOPC64_DPP16_NoDst_t16 op, VOP_DPP_Pseudo ps, + string opName = ps.OpName> + : VOPC64_DPP, VOP3_DPP_Enc_t16 { + let Inst{7-0} = ? ; + let Inst{14} = 0; } -class VOPC64_DPP8 op, VOP_Pseudo ps, string opName = ps.OpName> - : VOPC64_DPP8_Base { +class VOPC64_DPP8 + : VOP3_DPP8_Base { + Instruction Opcode = !cast(NAME); // Note ps is the non-dpp pseudo let hasSideEffects = ps.hasSideEffects; let Defs = ps.Defs; @@ -1416,15 +1439,30 @@ class VOPC64_DPP8 op, VOP_Pseudo ps, string opName = ps.OpName> } class VOPC64_DPP8_Dst op, VOP_Pseudo ps, string opName = ps.OpName> - : VOPC64_DPP8 { + : VOPC64_DPP8, VOP3_DPP8_Enc { bits<8> sdst; let Inst{7-0} = sdst; let Constraints = ""; } class VOPC64_DPP8_NoDst op, VOP_Pseudo ps, string opName = ps.OpName> - : VOPC64_DPP8 { + : VOPC64_DPP8, VOP3_DPP8_Enc { + let Inst{7-0} = ? ; + let Constraints = ""; +} + +class VOPC64_DPP8_Dst_t16 op, VOP_Pseudo ps, string opName = ps.OpName> + : VOPC64_DPP8, VOP3_DPP8_Enc_t16 { + bits<8> sdst; + let Inst{7-0} = sdst; + let Inst{14} = 0; + let Constraints = ""; +} + +class VOPC64_DPP8_NoDst_t16 op, VOP_Pseudo ps, string opName = ps.OpName> + : VOPC64_DPP8, VOP3_DPP8_Enc_t16 { let Inst{7-0} = ? ; + let Inst{14} = 0; let Constraints = ""; } @@ -1442,7 +1480,7 @@ multiclass VOPC_Real_Base op> { defvar ps64 = !cast(NAME#"_e64"); def _e32#Gen.Suffix : VOPC_Real, VOPCe; - def _e64#Gen.Suffix : VOP3_Real, + def _e64#Gen.Suffix : VOP3_Real_Gen, VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { // Encoding used for VOPC instructions encoded as VOP3 differs from // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. @@ -1508,13 +1546,25 @@ multiclass VOPC_Real_with_name op, string OpName, // the destination-less 32bit forms add it to the asmString here. VOPC_Real, VOPCe; - def _e64#Gen.Suffix : - VOP3_Real_Gen, - VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { - // Encoding used for VOPC instructions encoded as VOP3 differs from - // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. - bits<8> sdst; - let Inst{7-0} = sdst; + if ps64.Pfl.IsRealTrue16 then { + def _e64#Gen.Suffix : + VOP3_Real_Gen, + VOP3e_t16_gfx11_gfx12<{0, op}, ps64.Pfl> { + // Encoding used for VOPC instructions encoded as VOP3 differs from + // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. + bits<8> sdst; + let Inst{7-0} = sdst; + let Inst{14} = 0; + } + } else { + def _e64#Gen.Suffix : + VOP3_Real_Gen, + VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { + // Encoding used for VOPC instructions encoded as VOP3 differs from + // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. + bits<8> sdst; + let Inst{7-0} = sdst; + } } defm : VOPCInstAliases; @@ -1554,9 +1604,15 @@ multiclass VOPC_Real_with_name op, string OpName, if ps64.Pfl.HasExtVOP3DPP then { defvar psDPP = !cast(OpName #"_e64" #"_dpp"); - def _e64_dpp#Gen.Suffix : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name>, - SIMCInstr; - def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name>; + if ps64.Pfl.IsRealTrue16 then { + def _e64_dpp#Gen.Suffix : VOPC64_DPP16_Dst_t16<{0, op}, psDPP, asm_name>, + SIMCInstr; + def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_Dst_t16<{0, op}, ps64, asm_name>; + } else { + def _e64_dpp#Gen.Suffix : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name>, + SIMCInstr; + def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name>; + } } // end if ps64.Pfl.HasExtVOP3DPP } // End DecoderNamespace } // End AssemblerPredicate @@ -1693,11 +1749,23 @@ multiclass VOPC_Real_t16_gfx11 op, string asm_name, string OpName = NAME, string pseudo_mnemonic = ""> : VOPC_Real_t16; +multiclass VOPC_Real_t16_and_fake16_gfx11 op, string asm_name, + string OpName = NAME, string pseudo_mnemonic = ""> { + defm _t16: VOPC_Real_t16_gfx11; + defm _fake16: VOPC_Real_t16_gfx11; +} + multiclass VOPC_Real_t16_gfx11_gfx12 op, string asm_name, string OpName = NAME, string pseudo_mnemonic = ""> : VOPC_Real_t16, VOPC_Real_t16; +multiclass VOPC_Real_t16_and_fake16_gfx11_gfx12 op, string asm_name, + string OpName = NAME, string pseudo_mnemonic = ""> { + defm _t16: VOPC_Real_t16_gfx11_gfx12; + defm _fake16: VOPC_Real_t16_gfx11_gfx12; +} + multiclass VOPCX_Real_t16_gfx11 op, string asm_name, string OpName = NAME, string pseudo_mnemonic = ""> : VOPCX_Real_t16; @@ -1708,7 +1776,7 @@ multiclass VOPCX_Real_t16_gfx11_gfx12 op, string asm_name, VOPCX_Real_t16; defm V_CMP_F_F16_fake16 : VOPC_Real_t16_gfx11<0x000, "v_cmp_f_f16">; -defm V_CMP_LT_F16_fake16 : VOPC_Real_t16_gfx11_gfx12<0x001, "v_cmp_lt_f16">; +defm V_CMP_LT_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x001, "v_cmp_lt_f16">; defm V_CMP_EQ_F16_fake16 : VOPC_Real_t16_gfx11_gfx12<0x002, "v_cmp_eq_f16">; defm V_CMP_LE_F16_fake16 : VOPC_Real_t16_gfx11_gfx12<0x003, "v_cmp_le_f16">; defm V_CMP_GT_F16_fake16 : VOPC_Real_t16_gfx11_gfx12<0x004, "v_cmp_gt_f16">; diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index 930ed9a5e2d0b..3b5358b737aa4 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -2033,7 +2033,7 @@ def VOP2InfoTable : VOPInfoTable<"VOP2">; def VOP3InfoTable : VOPInfoTable<"VOP3">; class VOPC64Table : GenericTable { - let FilterClass = "VOPC64_" # Format # "_Base"; + let FilterClass = "VOPC64_" # Format; let CppTypeName = "VOPC64DPPInfo"; let Fields = ["Opcode"]; diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s index 1b9092d30b1b7..b51e54feadaa0 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s @@ -3428,112 +3428,127 @@ v_cmp_lg_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0 v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 // GFX11: v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x83,0x15,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] -v_cmp_lt_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3] -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3] +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_mirror -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_mirror +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_half_mirror -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_half_mirror +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shl:1 -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shl:1 +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shl:15 -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shl:15 +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shr:1 -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shr:1 +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shr:15 -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shr:15 +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_ror:1 -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_ror:1 +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s105, v1, v2 row_ror:15 -// W32: v_cmp_lt_f16_e64_dpp s105, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s105, v1.l, v2.l row_ror:15 +// W32: v_cmp_lt_f16_e64_dpp s105, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +v_cmp_lt_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W32: v_cmp_lt_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +v_cmp_lt_f16_e64_dpp vcc_hi, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_lt_f16_e64_dpp vcc_hi, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W32: v_cmp_lt_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +v_cmp_lt_f16_e64_dpp ttmp15, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_lt_f16_e64_dpp ttmp15, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_mirror -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W64: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W64: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// GFX11: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] +v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] + +v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp ttmp15, -v1.h, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: [0x7b,0x0a,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: [0x7a,0x0a,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: [0x7c,0x93,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] v_cmp_lt_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] // W32: v_cmp_lt_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s index 1efbd671cfaee..7da21422713ce 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s @@ -1252,44 +1252,59 @@ v_cmp_lg_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 // GFX11: v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x83,0x15,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] -v_cmp_lt_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp vcc_hi, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_hi, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W32: v_cmp_lt_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x02,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp ttmp15, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_lt_f16_e64_dpp ttmp15, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x02,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x02,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x02,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 -// GFX11: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x83,0x01,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x83,0x01,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp ttmp15, -v1.h, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: [0x7b,0x0a,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: [0x7a,0x0a,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: [0x7c,0x93,0x01,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] v_cmp_lt_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] // W32: v_cmp_lt_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s index cd720e286b902..d936d8ab5111d 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s @@ -5259,12 +5259,12 @@ v_cmp_lg_f64_e64 ttmp[14:15], -|src_scc|, -|exec| v_cmp_lg_f64_e64 null, 0xaf123456, -|vcc| clamp // GFX11: v_cmp_lg_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x25,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf] -v_cmp_lt_f16_e64 s5, v1, v2 -// W32: v_cmp_lt_f16_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +v_cmp_lt_f16_e64 s5, v1.l, v2.l +// W32: v_cmp_lt_f16_e64 s5, v1.l, v2.l ; encoding: [0x05,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] // W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction -v_cmp_lt_f16_e64 s5, v255, v255 -// W32: v_cmp_lt_f16_e64 s5, v255, v255 ; encoding: [0x05,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +v_cmp_lt_f16_e64 s5, v255.l, v255.l +// W32: v_cmp_lt_f16_e64 s5, v255.l, v255.l ; encoding: [0x05,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] // W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction v_cmp_lt_f16_e64 s5, s1, s2 @@ -5315,12 +5315,12 @@ v_cmp_lt_f16_e64 ttmp15, -src_scc, |vcc_lo| // W32: v_cmp_lt_f16_e64 ttmp15, -src_scc, |vcc_lo| ; encoding: [0x7b,0x02,0x01,0xd4,0xfd,0xd4,0x00,0x20] // W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction -v_cmp_lt_f16_e64 s[10:11], v1, v2 -// W64: v_cmp_lt_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +v_cmp_lt_f16_e64 s[10:11], v1.l, v2.l +// W64: v_cmp_lt_f16_e64 s[10:11], v1.l, v2.l ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] // W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction -v_cmp_lt_f16_e64 s[10:11], v255, v255 -// W64: v_cmp_lt_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +v_cmp_lt_f16_e64 s[10:11], v255.l, v255.l +// W64: v_cmp_lt_f16_e64 s[10:11], v255.l, v255.l ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] // W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction v_cmp_lt_f16_e64 s[10:11], s1, s2 @@ -5374,6 +5374,26 @@ v_cmp_lt_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| v_cmp_lt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp // GFX11: v_cmp_lt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x01,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00] +v_cmp_lt_f16_e64 vcc_lo, 0.5, -m0 +// W32: v_cmp_lt_f16_e64 vcc_lo, 0.5, -m0 ; encoding: [0x6a,0x00,0x01,0xd4,0xf0,0xfa,0x00,0x40] +// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction + +v_cmp_lt_f16_e64 s5, v1.h, v2.l +// W32: [0x05,0x08,0x01,0xd4,0x01,0x05,0x02,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cmp_lt_f16_e64 s5, v255.l, v255.h +// W32: [0x05,0x10,0x01,0xd4,0xff,0xff,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cmp_lt_f16_e64 s[10:11], v1.h, v2.l +// W64: [0x0a,0x08,0x01,0xd4,0x01,0x05,0x02,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction + +v_cmp_lt_f16_e64 s[10:11], v255.l, v255.h +// W64: [0x0a,0x10,0x01,0xd4,0xff,0xff,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction + v_cmp_lt_f32_e64 s5, v1, v2 // W32: v_cmp_lt_f32_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x11,0xd4,0x01,0x05,0x02,0x00] // W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s index a8d28b36c5acf..a39c2070e3262 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s @@ -5476,124 +5476,164 @@ v_cmp_lg_f64 vcc, 0xaf123456, v[254:255] // W64: v_cmp_lg_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4b,0x7c,0x56,0x34,0x12,0xaf] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v127, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, v127.l, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, s1, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, s1, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, s105, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, s105, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, vcc_lo, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, vcc_lo, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, vcc_hi, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, vcc_hi, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, ttmp15, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, ttmp15, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, m0, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, m0, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, exec_lo, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, exec_lo, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, exec_hi, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, exec_hi, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, null, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, null, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, -1, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, -1, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, 0.5, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, 0.5, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, src_scc, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, src_scc, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, 0xfe0b, v127 -// W32: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +v_cmp_lt_f16 vcc_lo, 0xfe0b, v127.l +// W32: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 -// W64: v_cmp_lt_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] +v_cmp_lt_f16 vcc, v1.l, v2.l +// W64: v_cmp_lt_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v127, v2 -// W64: v_cmp_lt_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] +v_cmp_lt_f16 vcc, v127.l, v2.l +// W64: v_cmp_lt_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, s1, v2 -// W64: v_cmp_lt_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, s1, v2.l +// W64: v_cmp_lt_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, s105, v2 -// W64: v_cmp_lt_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, s105, v2.l +// W64: v_cmp_lt_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, vcc_lo, v2 -// W64: v_cmp_lt_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, vcc_lo, v2.l +// W64: v_cmp_lt_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, vcc_hi, v2 -// W64: v_cmp_lt_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, vcc_hi, v2.l +// W64: v_cmp_lt_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, ttmp15, v2 -// W64: v_cmp_lt_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, ttmp15, v2.l +// W64: v_cmp_lt_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, m0, v2 -// W64: v_cmp_lt_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, m0, v2.l +// W64: v_cmp_lt_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, exec_lo, v2 -// W64: v_cmp_lt_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, exec_lo, v2.l +// W64: v_cmp_lt_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, exec_hi, v2 -// W64: v_cmp_lt_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, exec_hi, v2.l +// W64: v_cmp_lt_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, null, v2 -// W64: v_cmp_lt_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, null, v2.l +// W64: v_cmp_lt_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, -1, v2 -// W64: v_cmp_lt_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, -1, v2.l +// W64: v_cmp_lt_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, 0.5, v2 -// W64: v_cmp_lt_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, 0.5, v2.l +// W64: v_cmp_lt_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, src_scc, v2 -// W64: v_cmp_lt_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, src_scc, v2.l +// W64: v_cmp_lt_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, 0xfe0b, v127 -// W64: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +v_cmp_lt_f16 vcc, 0xfe0b, v127.l +// W64: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.h, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0x02,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.h, v2.l +// W64: v_cmp_lt_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0x02,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v127.h, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0x02,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v127.h, v2.l +// W64: v_cmp_lt_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0x02,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, 0.5, v127.l +// W32: v_cmp_lt_f16_e32 vcc_lo, 0.5, v127.l ; encoding: [0xf0,0xfe,0x02,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, 0.5, v127.l +// W64: v_cmp_lt_f16_e32 vcc, 0.5, v127.l ; encoding: [0xf0,0xfe,0x02,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, src_scc, v2.h +// W32: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0x03,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, src_scc, v2.h +// W64: v_cmp_lt_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0x03,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, 0xfe0b, v127.h +// W32: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, 0xfe0b, v127.h +// W64: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_lt_f32 vcc_lo, v1, v2 diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s index ac94795ff95ae..fdaa9a990cb9b 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s @@ -3588,116 +3588,220 @@ v_cmp_lg_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound // W64: v_cmp_lg_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x2b,0x7c,0xff,0x6f,0xf5,0x30] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_mirror -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_mirror +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_half_mirror -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_half_mirror +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:1 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:15 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:15 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:1 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:15 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:15 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:1 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:15 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:15 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x09,0x13] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x09,0x13] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// W32: v_cmp_lt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xf5,0x30] +v_cmp_lt_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 +// W32: v_cmp_lt_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xf5,0x30] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] -// W64: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] -// W64: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_mirror -// W64: v_cmp_lt_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_mirror +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_half_mirror -// W64: v_cmp_lt_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_half_mirror +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_shl:1 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_shl:15 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:15 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_shr:1 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_shr:15 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:15 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_ror:1 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_ror:15 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:15 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W64: v_cmp_lt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +v_cmp_lt_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x09,0x13] +v_cmp_lt_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x09,0x13] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// W64: v_cmp_lt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xf5,0x30] +v_cmp_lt_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 +// W64: v_cmp_lt_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xf5,0x30] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_lt_f16 vcc_lo, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: v_cmp_lt_f16 vcc, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x5f,0x01,0x01] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_lt_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_lt_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: v_cmp_lt_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xf5,0x30] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: v_cmp_lt_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xf5,0x30] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_lt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s index 4e97456258351..97ad419a79ca8 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s @@ -772,28 +772,52 @@ v_cmp_lg_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 // W64: v_cmp_lg_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x2b,0x7c,0xff,0x00,0x00,0x00] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// W32: v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +v_cmp_lt_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] +// W32: v_cmp_lt_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W64: v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// W64: v_cmp_lt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +v_cmp_lt_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] +// W64: v_cmp_lt_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16 vcc_lo, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16 vcc, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_lt_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: v_cmp_lt_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: v_cmp_lt_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_lt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s index 4b97d276d5561..c48bff454deed 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s @@ -982,71 +982,137 @@ v_cmp_lg_f16_e32 vcc_lo, vcc_hi, v255 v_cmp_lg_f16_e32 vcc_lo, vcc_lo, v255 // GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16_e32 vcc, v1, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc, v1.h, v255.h +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v127, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc, v1.l, v255.l +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v128, v2 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc, v127.h, v255.h +// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v127.l, v255.l +// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] +v_cmp_lt_f16_e32 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.h, v2.h +// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.l, v2.l +// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, vcc_hi, v255.h +// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, vcc_hi, v255.l +// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, vcc_lo, v255.h +// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, vcc_lo, v255.l +// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, v1.h, v255.h // GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0] +v_cmp_lt_f16_e32 vcc_lo, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] // GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, vcc_hi, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, vcc_lo, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v1.l, v255.l +// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v1, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v127.h, v255.h +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v127, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v127.l, v255.l +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v128, v2 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v128.h, v2.h +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v255 -// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, v128.l, v2.l +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v255.h +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v255.l +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v255.h +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v255.l +// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction v_cmp_lt_i16_e32 vcc, v1, v255 // GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s index 49a3f8ad63e7e..dc0bf7663ac17 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s @@ -982,71 +982,137 @@ v_cmp_lg_f16 vcc, vcc_lo, v255 v_cmp_lg_f16 vcc, vcc_lo, v255 // GFX11: v_cmp_lg_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x05,0xd4,0x6a,0xfe,0x03,0x00] -v_cmp_lt_f16 vcc, v1, v255 -// GFX11: v_cmp_lt_f16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00] +v_cmp_lt_f16 vcc, v1.h, v255.h +// GFX11: v_cmp_lt_f16_e64 vcc, v1.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x01,0xff,0x03,0x00] -v_cmp_lt_f16 vcc, v1, v255 -// GFX11: v_cmp_lt_f16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00] +v_cmp_lt_f16 vcc, v1.h, v255.h +// GFX11: v_cmp_lt_f16_e64 vcc, v1.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x01,0xff,0x03,0x00] -v_cmp_lt_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_cmp_lt_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_cmp_lt_f16 vcc, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_cmp_lt_f16 vcc, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_cmp_lt_f16 vcc, v127, v255 -// GFX11: v_cmp_lt_f16_e64 vcc, v127, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x7f,0xff,0x03,0x00] +v_cmp_lt_f16 vcc, v1.l, v255.l +// GFX11: v_cmp_lt_f16_e64 vcc, v1.l, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00] -v_cmp_lt_f16 vcc, v127, v255 -// GFX11: v_cmp_lt_f16_e64 vcc, v127, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x7f,0xff,0x03,0x00] +v_cmp_lt_f16 vcc, v1.l, v255.l +// GFX11: v_cmp_lt_f16_e64 vcc, v1.l, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00] -v_cmp_lt_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_cmp_lt_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_cmp_lt_f16 vcc, v127, v255 quad_perm:[3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_cmp_lt_f16 vcc, v127, v255 quad_perm:[3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_cmp_lt_f16 vcc, v128, v2 -// GFX11: v_cmp_lt_f16_e64 vcc, v128, v2 ; encoding: [0x6a,0x00,0x01,0xd4,0x80,0x05,0x02,0x00] +v_cmp_lt_f16 vcc, v127.h, v255.h +// GFX11: v_cmp_lt_f16_e64 vcc, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x7f,0xff,0x03,0x00] -v_cmp_lt_f16 vcc, v128, v2 -// GFX11: v_cmp_lt_f16_e64 vcc, v128, v2 ; encoding: [0x6a,0x00,0x01,0xd4,0x80,0x05,0x02,0x00] +v_cmp_lt_f16 vcc, v127.h, v255.h +// GFX11: v_cmp_lt_f16_e64 vcc, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x7f,0xff,0x03,0x00] -v_cmp_lt_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] -v_cmp_lt_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] -v_cmp_lt_f16 vcc, v128, v2 quad_perm:[3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] -v_cmp_lt_f16 vcc, v128, v2 quad_perm:[3,2,1,0] -// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] -v_cmp_lt_f16 vcc, vcc_hi, v255 -// GFX11: v_cmp_lt_f16_e64 vcc, vcc_hi, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x6b,0xfe,0x03,0x00] +v_cmp_lt_f16 vcc, v127.l, v255.l +// GFX11: v_cmp_lt_f16_e64 vcc, v127.l, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x7f,0xff,0x03,0x00] -v_cmp_lt_f16 vcc, vcc_hi, v255 -// GFX11: v_cmp_lt_f16_e64 vcc, vcc_hi, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x6b,0xfe,0x03,0x00] +v_cmp_lt_f16 vcc, v127.l, v255.l +// GFX11: v_cmp_lt_f16_e64 vcc, v127.l, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x7f,0xff,0x03,0x00] -v_cmp_lt_f16 vcc, vcc_lo, v255 -// GFX11: v_cmp_lt_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x6a,0xfe,0x03,0x00] +v_cmp_lt_f16 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] -v_cmp_lt_f16 vcc, vcc_lo, v255 -// GFX11: v_cmp_lt_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x6a,0xfe,0x03,0x00] +v_cmp_lt_f16 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] + +v_cmp_lt_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] + +v_cmp_lt_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] + +v_cmp_lt_f16 vcc, v128.h, v2.h +// GFX11: v_cmp_lt_f16_e64 vcc, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x80,0x05,0x02,0x00] + +v_cmp_lt_f16 vcc, v128.h, v2.h +// GFX11: v_cmp_lt_f16_e64 vcc, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x80,0x05,0x02,0x00] + +v_cmp_lt_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] + +v_cmp_lt_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] + +v_cmp_lt_f16 vcc, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] + +v_cmp_lt_f16 vcc, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] + +v_cmp_lt_f16 vcc, v128.l, v2.l +// GFX11: v_cmp_lt_f16_e64 vcc, v128.l, v2.l ; encoding: [0x6a,0x00,0x01,0xd4,0x80,0x05,0x02,0x00] + +v_cmp_lt_f16 vcc, v128.l, v2.l +// GFX11: v_cmp_lt_f16_e64 vcc, v128.l, v2.l ; encoding: [0x6a,0x00,0x01,0xd4,0x80,0x05,0x02,0x00] + +v_cmp_lt_f16 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] + +v_cmp_lt_f16 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] + +v_cmp_lt_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] + +v_cmp_lt_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX11: v_cmp_lt_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] + +v_cmp_lt_f16 vcc, vcc_hi, v255.h +// GFX11: v_cmp_lt_f16_e64 vcc, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x01,0xd4,0x6b,0xfe,0x03,0x00] + +v_cmp_lt_f16 vcc, vcc_hi, v255.h +// GFX11: v_cmp_lt_f16_e64 vcc, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x01,0xd4,0x6b,0xfe,0x03,0x00] + +v_cmp_lt_f16 vcc, vcc_hi, v255.l +// GFX11: v_cmp_lt_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x6b,0xfe,0x03,0x00] + +v_cmp_lt_f16 vcc, vcc_hi, v255.l +// GFX11: v_cmp_lt_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x6b,0xfe,0x03,0x00] + +v_cmp_lt_f16 vcc, vcc_lo, v255.h +// GFX11: v_cmp_lt_f16_e64 vcc, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x01,0xd4,0x6a,0xfe,0x03,0x00] + +v_cmp_lt_f16 vcc, vcc_lo, v255.h +// GFX11: v_cmp_lt_f16_e64 vcc, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x01,0xd4,0x6a,0xfe,0x03,0x00] + +v_cmp_lt_f16 vcc, vcc_lo, v255.l +// GFX11: v_cmp_lt_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x6a,0xfe,0x03,0x00] + +v_cmp_lt_f16 vcc, vcc_lo, v255.l +// GFX11: v_cmp_lt_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x6a,0xfe,0x03,0x00] v_cmp_lt_i16 vcc, v1, v255 // GFX11: v_cmp_lt_i16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x31,0xd4,0x01,0xff,0x03,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s index b08dc39c76386..177b994d5ad06 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s @@ -4522,12 +4522,12 @@ v_cmp_lg_f64_e64 ttmp[14:15], -|src_scc|, -|exec| v_cmp_lg_f64_e64 null, 0xaf123456, -|vcc| clamp // GFX12: v_cmp_lg_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x25,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf] -v_cmp_lt_f16_e64 s5, v1, v2 -// W32: v_cmp_lt_f16_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +v_cmp_lt_f16_e64 s5, v1.l, v2.l +// W32: v_cmp_lt_f16_e64 s5, v1.l, v2.l ; encoding: [0x05,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] // W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction -v_cmp_lt_f16_e64 s5, v255, v255 -// W32: v_cmp_lt_f16_e64 s5, v255, v255 ; encoding: [0x05,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +v_cmp_lt_f16_e64 s5, v255.l, v255.l +// W32: v_cmp_lt_f16_e64 s5, v255.l, v255.l ; encoding: [0x05,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] // W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction v_cmp_lt_f16_e64 s5, s1, s2 @@ -4578,13 +4578,13 @@ v_cmp_lt_f16_e64 ttmp15, -src_scc, |vcc_lo| // W32: v_cmp_lt_f16_e64 ttmp15, -src_scc, |vcc_lo| ; encoding: [0x7b,0x02,0x01,0xd4,0xfd,0xd4,0x00,0x20] // W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction -v_cmp_lt_f16_e64 s[10:11], v1, v2 -// W64: v_cmp_lt_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] -// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction +v_cmp_lt_f16_e64 s10, v1.l, v2.l +// W32: v_cmp_lt_f16_e64 s10, v1.l, v2.l ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction -v_cmp_lt_f16_e64 s[10:11], v255, v255 -// W64: v_cmp_lt_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] -// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction +v_cmp_lt_f16_e64 s10, v255.l, v255.l +// W32: v_cmp_lt_f16_e64 s10, v255.l, v255.l ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction v_cmp_lt_f16_e64 s[10:11], s1, s2 // W64: v_cmp_lt_f16_e64 s[10:11], s1, s2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x04,0x00,0x00] @@ -4637,6 +4637,26 @@ v_cmp_lt_f16_e64 ttmp[14:15], -src_scc, |vcc_lo| v_cmp_lt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp // GFX12: v_cmp_lt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x01,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00] +v_cmp_lt_f16_e64 s5, v1.h, v2.l +// W32: v_cmp_lt_f16_e64 s5, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x01,0xd4,0x01,0x05,0x02,0x00] +// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction + +v_cmp_lt_f16_e64 s5, v255.l, v255.h +// W32: v_cmp_lt_f16_e64 s5, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x01,0xd4,0xff,0xff,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction + +v_cmp_lt_f16_e64 s[10:11], v1.h, v2.l +// W64: v_cmp_lt_f16_e64 s[10:11], v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x01,0xd4,0x01,0x05,0x02,0x00] +// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction + +v_cmp_lt_f16_e64 s[10:11], v255.l, v255.h +// W64: v_cmp_lt_f16_e64 s[10:11], v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x01,0xd4,0xff,0xff,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction + +v_cmp_lt_f16_e64 vcc_lo, 0.5, -m0 +// W32: v_cmp_lt_f16_e64 vcc_lo, 0.5, -m0 ; encoding: [0x6a,0x00,0x01,0xd4,0xf0,0xfa,0x00,0x40] +// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction + v_cmp_lt_f32_e64 s5, v1, v2 // W32: v_cmp_lt_f32_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x11,0xd4,0x01,0x05,0x02,0x00] // W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s index 98462309b2a3b..8908f18ac29bb 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s @@ -3448,128 +3448,143 @@ v_cmp_lg_f32_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0 v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 // GFX12: v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x83,0x15,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] -v_cmp_lt_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, s2 quad_perm:[3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp s5, v1, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, s2 quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, 2.0 quad_perm:[3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp s5, v1, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, 2.0 quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3] -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3] +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_mirror -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_mirror +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_half_mirror -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_half_mirror +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shl:1 -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shl:1 +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shl:15 -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shl:15 +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shr:1 -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shr:1 +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shr:15 -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shr:15 +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, v2 row_ror:1 -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_ror:1 +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s105, v1, v2 row_ror:15 -// W32: v_cmp_lt_f16_e64_dpp s105, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s105, v1.l, v2.l row_ror:15 +// W32: v_cmp_lt_f16_e64_dpp s105, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +v_cmp_lt_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W32: v_cmp_lt_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +v_cmp_lt_f16_e64_dpp vcc_hi, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_lt_f16_e64_dpp vcc_hi, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W32: v_cmp_lt_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +v_cmp_lt_f16_e64_dpp ttmp15, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_lt_f16_e64_dpp ttmp15, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, s2 quad_perm:[3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, s2 quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, 2.0 quad_perm:[3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, 2.0 quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_mirror -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W64: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W64: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// GFX12: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] +v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] + +v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x93,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] + +v_cmp_lt_f16_e64_dpp ttmp15, -v1.h, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_lt_f16_e64_dpp ttmp15, -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x0a,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x0a,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction v_cmp_lt_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] // W32: v_cmp_lt_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s index 4617914b502b3..80ac6aa9af00e 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s @@ -1544,60 +1544,75 @@ v_cmp_lg_f32_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 // GFX12: v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x83,0x15,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] -v_cmp_lt_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, s2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp s5, v1, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s5, v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s5, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp s5, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s5, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp s5, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp vcc_hi, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_hi, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W32: v_cmp_lt_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x02,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp ttmp15, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_lt_f16_e64_dpp ttmp15, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x02,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, s2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[10:11], v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s[10:11], v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x02,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +v_cmp_lt_f16_e64_dpp ttmp14, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_lt_f16_e64_dpp ttmp14, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x02,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] +// GFX12: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x83,0x01,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +v_cmp_lt_f16_e64_dpp ttmp15, -v1.h, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_lt_f16_e64_dpp ttmp15, -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x0a,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction + +v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x0a,0x01,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction -v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 -// GFX12: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x83,0x01,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x93,0x01,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] v_cmp_lt_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] // W32: v_cmp_lt_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s index 1987f5a5fa2fc..7991231aa68ed 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s @@ -4708,124 +4708,156 @@ v_cmp_lg_f64 vcc, 0xaf123456, v[254:255] // W64: v_cmp_lg_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4b,0x7c,0x56,0x34,0x12,0xaf] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v127, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, v127.l, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, s1, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, s1, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, s105, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, s105, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, vcc_lo, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, vcc_lo, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, vcc_hi, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, vcc_hi, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, ttmp15, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, ttmp15, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, m0, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, m0, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, exec_lo, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, exec_lo, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, exec_hi, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, exec_hi, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, null, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, null, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, -1, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, -1, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, 0.5, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, 0.5, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, src_scc, v2 -// W32: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc_lo, src_scc, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0x02,0x7c] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, 0xfe0b, v127 -// W32: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +v_cmp_lt_f16 vcc_lo, 0xfe0b, v127.l +// W32: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 -// W64: v_cmp_lt_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] +v_cmp_lt_f16 vcc, v1.l, v2.l +// W64: v_cmp_lt_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v127, v2 -// W64: v_cmp_lt_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] +v_cmp_lt_f16 vcc, v127.l, v2.l +// W64: v_cmp_lt_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, s1, v2 -// W64: v_cmp_lt_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, s1, v2.l +// W64: v_cmp_lt_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, s105, v2 -// W64: v_cmp_lt_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, s105, v2.l +// W64: v_cmp_lt_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, vcc_lo, v2 -// W64: v_cmp_lt_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, vcc_lo, v2.l +// W64: v_cmp_lt_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, vcc_hi, v2 -// W64: v_cmp_lt_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, vcc_hi, v2.l +// W64: v_cmp_lt_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, ttmp15, v2 -// W64: v_cmp_lt_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, ttmp15, v2.l +// W64: v_cmp_lt_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, m0, v2 -// W64: v_cmp_lt_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, m0, v2.l +// W64: v_cmp_lt_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, exec_lo, v2 -// W64: v_cmp_lt_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, exec_lo, v2.l +// W64: v_cmp_lt_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, exec_hi, v2 -// W64: v_cmp_lt_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, exec_hi, v2.l +// W64: v_cmp_lt_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, null, v2 -// W64: v_cmp_lt_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, null, v2.l +// W64: v_cmp_lt_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, -1, v2 -// W64: v_cmp_lt_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, -1, v2.l +// W64: v_cmp_lt_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, 0.5, v2 -// W64: v_cmp_lt_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, 0.5, v2.l +// W64: v_cmp_lt_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, src_scc, v2 -// W64: v_cmp_lt_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] +v_cmp_lt_f16 vcc, src_scc, v2.l +// W64: v_cmp_lt_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0x02,0x7c] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, 0xfe0b, v127 -// W64: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +v_cmp_lt_f16 vcc, 0xfe0b, v127.l +// W64: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.h, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0x02,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.h, v2.l +// W64: v_cmp_lt_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0x02,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v127.h, v2.l +// W32: v_cmp_lt_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0x02,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v127.h, v2.l +// W64: v_cmp_lt_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0x02,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, src_scc, v2.h +// W32: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0x03,0x7c] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, src_scc, v2.h +// W64: v_cmp_lt_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0x03,0x7c] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, 0xfe0b, v127.h +// W32: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, 0xfe0b, v127.h +// W64: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_lt_f32 vcc_lo, v1, v2 diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s index 4723ab1fc7c74..54c3df6b139af 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s @@ -3140,116 +3140,212 @@ v_cmp_lg_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound // W64: v_cmp_lg_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x2b,0x7c,0xff,0x6f,0xf5,0x30] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_mirror -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_mirror +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_half_mirror -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_half_mirror +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:1 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:15 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:15 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:1 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:15 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:15 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:1 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:15 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:15 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x09,0x13] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x09,0x13] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// W32: v_cmp_lt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xf5,0x30] +v_cmp_lt_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 +// W32: v_cmp_lt_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xf5,0x30] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] -// W64: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] -// W64: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_mirror -// W64: v_cmp_lt_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_mirror +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_half_mirror -// W64: v_cmp_lt_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_half_mirror +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_shl:1 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_shl:15 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:15 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_shr:1 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_shr:15 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:15 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_ror:1 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_ror:15 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:15 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf -// W64: v_cmp_lt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +v_cmp_lt_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +v_cmp_lt_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 -// W64: v_cmp_lt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x09,0x13] +v_cmp_lt_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x09,0x13] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 -// W64: v_cmp_lt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xf5,0x30] +v_cmp_lt_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 +// W64: v_cmp_lt_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xf5,0x30] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: v_cmp_lt_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: v_cmp_lt_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: v_cmp_lt_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xf5,0x30] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: v_cmp_lt_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xf5,0x30] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_lt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s index 01c66fc5ff24a..7414795639205 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s @@ -676,28 +676,44 @@ v_cmp_lg_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 // W64: v_cmp_lg_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x2b,0x7c,0xff,0x00,0x00,0x00] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W32: v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// W32: v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +v_cmp_lt_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] +// W32: v_cmp_lt_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 -// W64: v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_lt_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 -// W64: v_cmp_lt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +v_cmp_lt_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] +// W64: v_cmp_lt_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: v_cmp_lt_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: v_cmp_lt_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: v_cmp_lt_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode + +v_cmp_lt_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: v_cmp_lt_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode v_cmp_lt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s index e603e7388a684..8944a76fcc801 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s @@ -916,71 +916,137 @@ v_cmp_lg_f16_e32 vcc_lo, vcc_hi, v255 v_cmp_lg_f16_e32 vcc_lo, vcc_lo, v255 // GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16_e32 vcc, v1, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc, v1.h, v255.h +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v127, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc, v1.l, v255.l +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v128, v2 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc, v127.h, v255.h +// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] +v_cmp_lt_f16_e32 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v127.l, v255.l +// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.h, v2.h +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.l, v2.l +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, vcc_hi, v255.h +// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, vcc_hi, v255.l +// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, vcc_lo, v255.h +// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc, vcc_lo, v255.l +// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, v1.h, v255.h // GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0] +v_cmp_lt_f16_e32 vcc_lo, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] // GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, vcc_hi, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v1.h, v255.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc, vcc_lo, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v1.l, v255.l +// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v1, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v127.h, v255.h +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v127, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v127.h, v255.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v127.l, v255.l +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v128, v2 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction +v_cmp_lt_f16_e32 vcc_lo, v128.h, v2.h +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction -v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v255 -// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16_e32 vcc_lo, v128.h, v2.h quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, v128.l, v2.l +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v255.h +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v255.l +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v255.h +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction + +v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v255.l +// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction v_cmp_lt_i16_e32 vcc, v1, v255 // GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s index e56c46bb55448..d37859f2802b8 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s @@ -1224,93 +1224,181 @@ v_cmp_lg_f16 vcc_lo, vcc_lo, v255 // W32: v_cmp_lg_f16_e64 vcc_lo, vcc_lo, v255 ; encoding: [0x6a,0x00,0x05,0xd4,0x6a,0xfe,0x03,0x00] // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode -v_cmp_lt_f16 vcc, v1, v255 -// W64: v_cmp_lt_f16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00] -// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16 vcc, v1.h, v255.h +// W64: v_cmp_lt_f16_e64 vcc, v1.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x01,0xff,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc, v1, v255 quad_perm:[3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v1.h, v255.h quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc, v127, v255 -// W64: v_cmp_lt_f16_e64 vcc, v127, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x7f,0xff,0x03,0x00] -// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16 vcc, v1.l, v255.l +// W64: v_cmp_lt_f16_e64 vcc, v1.l, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc, v127, v255 quad_perm:[3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v1.l, v255.l quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc, v128, v2 -// W64: v_cmp_lt_f16_e64 vcc, v128, v2 ; encoding: [0x6a,0x00,0x01,0xd4,0x80,0x05,0x02,0x00] -// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16 vcc, v127.h, v255.h +// W64: v_cmp_lt_f16_e64 vcc, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x7f,0xff,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +v_cmp_lt_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] // W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc, v128, v2 quad_perm:[3,2,1,0] -// W64: v_cmp_lt_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc, v127.h, v255.h quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] // W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc, vcc_hi, v255 -// W64: v_cmp_lt_f16_e64 vcc, vcc_hi, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x6b,0xfe,0x03,0x00] -// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16 vcc, v127.l, v255.l +// W64: v_cmp_lt_f16_e64 vcc, v127.l, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x7f,0xff,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc, vcc_lo, v255 -// W64: v_cmp_lt_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x6a,0xfe,0x03,0x00] -// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, v1, v255 -// W32: v_cmp_lt_f16_e64 vcc_lo, v1, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00] -// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc, v128.h, v2.h +// W64: v_cmp_lt_f16_e64 vcc, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x80,0x05,0x02,0x00] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc, v128.h, v2.h quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc, v128.l, v2.l +// W64: v_cmp_lt_f16_e64 vcc, v128.l, v2.l ; encoding: [0x6a,0x00,0x01,0xd4,0x80,0x05,0x02,0x00] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0] +// W64: v_cmp_lt_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc, vcc_hi, v255.h +// W64: v_cmp_lt_f16_e64 vcc, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x01,0xd4,0x6b,0xfe,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc, vcc_hi, v255.l +// W64: v_cmp_lt_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x6b,0xfe,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc, vcc_lo, v255.h +// W64: v_cmp_lt_f16_e64 vcc, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x01,0xd4,0x6a,0xfe,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc, vcc_lo, v255.l +// W64: v_cmp_lt_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x6a,0xfe,0x03,0x00] +// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] +v_cmp_lt_f16 vcc_lo, v1.h, v255.h +// W32: v_cmp_lt_f16_e64 vcc_lo, v1.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x01,0xff,0x03,0x00] // W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc_lo, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, v127, v255 -// W32: v_cmp_lt_f16_e64 vcc_lo, v127, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x7f,0xff,0x03,0x00] -// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16 vcc_lo, v1.h, v255.h quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +v_cmp_lt_f16 vcc_lo, v1.l, v255.l +// W32: v_cmp_lt_f16_e64 vcc_lo, v1.l, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00] // W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc_lo, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, v128, v2 -// W32: v_cmp_lt_f16_e64 vcc_lo, v128, v2 ; encoding: [0x6a,0x00,0x01,0xd4,0x80,0x05,0x02,0x00] -// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16 vcc_lo, v1.l, v255.l quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +v_cmp_lt_f16 vcc_lo, v127.h, v255.h +// W32: v_cmp_lt_f16_e64 vcc_lo, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x7f,0xff,0x03,0x00] // W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0] -// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +v_cmp_lt_f16 vcc_lo, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] // W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, vcc_hi, v255 -// W32: v_cmp_lt_f16_e64 vcc_lo, vcc_hi, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x6b,0xfe,0x03,0x00] -// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16 vcc_lo, v127.h, v255.h quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction -v_cmp_lt_f16 vcc_lo, vcc_lo, v255 -// W32: v_cmp_lt_f16_e64 vcc_lo, vcc_lo, v255 ; encoding: [0x6a,0x00,0x01,0xd4,0x6a,0xfe,0x03,0x00] -// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode +v_cmp_lt_f16 vcc_lo, v127.l, v255.l +// W32: v_cmp_lt_f16_e64 vcc_lo, v127.l, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x7f,0xff,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, v128.h, v2.h +// W32: v_cmp_lt_f16_e64 vcc_lo, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0x80,0x05,0x02,0x00] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, v128.h, v2.h quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, v128.l, v2.l +// W32: v_cmp_lt_f16_e64 vcc_lo, v128.l, v2.l ; encoding: [0x6a,0x00,0x01,0xd4,0x80,0x05,0x02,0x00] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0] +// W32: v_cmp_lt_f16_e64_dpp vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, vcc_hi, v255.h +// W32: v_cmp_lt_f16_e64 vcc_lo, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x01,0xd4,0x6b,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, vcc_hi, v255.l +// W32: v_cmp_lt_f16_e64 vcc_lo, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x6b,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, vcc_lo, v255.h +// W32: v_cmp_lt_f16_e64 vcc_lo, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x01,0xd4,0x6a,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction + +v_cmp_lt_f16 vcc_lo, vcc_lo, v255.l +// W32: v_cmp_lt_f16_e64 vcc_lo, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x01,0xd4,0x6a,0xfe,0x03,0x00] +// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction v_cmp_lt_i16 vcc, v1, v255 // W64: v_cmp_lt_i16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x31,0xd4,0x01,0xff,0x03,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt index a8974243b755e..4e2527cc2fa2f 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32,W32-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32,W32-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,W64-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff # W32: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] @@ -1765,59 +1765,100 @@ # GFX11: v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x15,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] 0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s104, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] 0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01 -# W32: v_cmp_lt_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] -# W64: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +# W32-REAL16: v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +# W64-REAL16: v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] 0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13 -# W32: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] -# W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W32-REAL16: v_cmp_lt_f16_e64_dpp ttmp14, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] 0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30 -# GFX11: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W32-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W64-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] + +0x7a,0x0a,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13 +# W32-REAL16: v_cmp_lt_f16_e64_dpp ttmp14, -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x0a,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x0a,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] + +0x7c,0x93,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30 +# W32-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x93,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W64-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x93,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] 0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff # W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt index 902cbc2d6f20f..f399fe7f0aef4 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32,W32-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32,W32-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,W64-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 # W32: v_cmp_class_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] @@ -613,23 +613,46 @@ # GFX11: v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x15,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] 0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s104, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] 0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16_e64_dpp ttmp14, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] 0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00 -# GFX11: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W32-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +0x7a,0x0a,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05 +# W32-REAL16: v_cmp_lt_f16_e64_dpp ttmp14, -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x0a,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x0a,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +0x7c,0x93,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00 +# W32-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x93,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x93,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] 0x0a,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 # W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt index ac1263916df85..350087218d366 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32,W32-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32,W32-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,W64-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00 # W32: v_cmp_class_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] @@ -2708,12 +2708,16 @@ # GFX11: v_cmp_lg_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x25,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf] 0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00 -# W32: v_cmp_lt_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] -# W64: v_cmp_lt_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +# W32-REAL16: v_cmp_lt_f16_e64 s10, v1.l, v2.l ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +# W64-REAL16: v_cmp_lt_f16_e64 s[10:11], v1.l, v2.l ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] 0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00 -# W32: v_cmp_lt_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] -# W64: v_cmp_lt_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +# W32-REAL16: v_cmp_lt_f16_e64 s10, v255.l, v255.l ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +# W64-REAL16: v_cmp_lt_f16_e64 s[10:11], v255.l, v255.l ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] 0x0a,0x00,0x01,0xd4,0x01,0x04,0x00,0x00 # W32: v_cmp_lt_f16_e64 s10, s1, s2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x04,0x00,0x00] @@ -2766,6 +2770,18 @@ 0x7c,0x83,0x01,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00 # GFX11: v_cmp_lt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x01,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00] +0x0a,0x08,0x01,0xd4,0x01,0x05,0x02,0x00 +# W32-REAL16: v_cmp_lt_f16_e64 s10, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x01,0xd4,0x01,0x05,0x02,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +# W64-REAL16: v_cmp_lt_f16_e64 s[10:11], v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x01,0xd4,0x01,0x05,0x02,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] + +0x0a,0x10,0x01,0xd4,0xff,0xff,0x03,0x00 +# W32-REAL16: v_cmp_lt_f16_e64 s10, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x01,0xd4,0xff,0xff,0x03,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +# W64-REAL16: v_cmp_lt_f16_e64 s[10:11], v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x01,0xd4,0xff,0xff,0x03,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] + 0x0a,0x00,0x11,0xd4,0x01,0x05,0x02,0x00 # W32: v_cmp_lt_f32_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x11,0xd4,0x01,0x05,0x02,0x00] # W64: v_cmp_lt_f32_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x11,0xd4,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt index 046c8f07e16fa..7f2de110be37d 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-FAKE16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0x01,0x05,0xfa,0x7c # W32: v_cmp_class_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] @@ -2741,64 +2741,144 @@ # W64: v_cmp_lg_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4b,0x7c,0x56,0x34,0x12,0xaf] 0x01,0x05,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] + 0x7f,0x05,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] + 0x01,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] + 0x69,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] + 0x6a,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] + 0x6b,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] + 0x7b,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] + 0x7d,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] + 0x7e,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] + 0x7f,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] + 0x7c,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] + 0xc1,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] + 0xf0,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] + 0xfd,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] + 0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00 -# W32: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] -# W64: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] + + +0x81,0x05,0x02,0x7c +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x02,0x7c] + + +0xff,0x05,0x02,0x7c +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x02,0x7c] + + +0xf0,0xfe,0x02,0x7c +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, 0.5, v127.l ; encoding: [0xf0,0xfe,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, 0.5, v127.l ; encoding: [0xf0,0xfe,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, 0.5, v127 ; encoding: [0xf0,0xfe,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, 0.5, v127 ; encoding: [0xf0,0xfe,0x02,0x7c] + + +0xfd,0x04,0x03,0x7c +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0x03,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0x03,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0x03,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0x03,0x7c] + + +0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00 +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] + 0x01,0x05,0x22,0x7c # W32: v_cmp_lt_f32_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x22,0x7c] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt index a5f52e62fda44..da691eebd06c4 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-FAKE16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff # W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] @@ -1797,60 +1797,106 @@ # W64: v_cmp_lg_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2b,0x7c,0xff,0x6f,0xfd,0x30] 0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01 -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13 -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] 0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30 -# W32: v_cmp_lt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] -# W64: v_cmp_lt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] +# W64-REAL16: v_cmp_lt_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] +# W64-FAKE16: v_cmp_lt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] + +0xfa,0xfe,0x02,0x7c,0x7f,0x5f,0x01,0x01 +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x5f,0x01,0x01] +# W64-REAL16: v_cmp_lt_f16 vcc, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x5f,0x01,0x01] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v127, v127 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x5f,0x01,0x01] +# W64-FAKE16: v_cmp_lt_f16 vcc, v127, v127 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x5f,0x01,0x01] + +0xfa,0x04,0x03,0x7c,0x81,0x60,0x01,0x13 +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x01,0x13] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_lt_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x01,0x13] + +0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xfd,0x30 +# W32-REAL16: v_cmp_lt_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xfd,0x30] +# W64-REAL16: v_cmp_lt_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xfd,0x30] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xfd,0x30] +# W64-FAKE16: v_cmp_lt_f16 vcc, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xfd,0x30] 0xfa,0x04,0x22,0x7c,0x01,0x1b,0x00,0xff # W32: v_cmp_lt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt index 261ad14af9010..998f8ea6618ca 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-FAKE16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05 # W32: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] @@ -261,12 +261,34 @@ # W64: v_cmp_lg_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2b,0x7c,0xff,0x00,0x00,0x00] 0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] 0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00 -# W32: v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] -# W64: v_cmp_lt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] + +0xe9,0xfe,0x02,0x7c,0x7f,0x77,0x39,0x05 +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16 vcc, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16 vcc, v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x02,0x7c,0x7f,0x77,0x39,0x05] + +0xe9,0x04,0x03,0x7c,0x81,0x77,0x39,0x05 +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] + +0xea,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00 +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16 vcc, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] 0xe9,0x04,0x22,0x7c,0x01,0x77,0x39,0x05 # W32: v_cmp_lt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x22,0x7c,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt index 62d235e1d8206..aa3d350134424 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,W32-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,W32-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,W64-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00 # W32: v_cmp_class_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00] @@ -2327,12 +2327,16 @@ # GFX12: v_cmp_lg_f64_e64 null, 0xaf123456, -|vcc| clamp ; encoding: [0x7c,0x82,0x25,0xd4,0xff,0xd4,0x00,0x40,0x56,0x34,0x12,0xaf] 0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00 -# W32: v_cmp_lt_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] -# W64: v_cmp_lt_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +# W32-REAL16: v_cmp_lt_f16_e64 s10, v1.l, v2.l ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +# W64-REAL16: v_cmp_lt_f16_e64 s[10:11], v1.l, v2.l ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] 0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00 -# W32: v_cmp_lt_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] -# W64: v_cmp_lt_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +# W32-REAL16: v_cmp_lt_f16_e64 s10, v255.l, v255.l ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +# W64-REAL16: v_cmp_lt_f16_e64 s[10:11], v255.l, v255.l ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] 0x0a,0x00,0x01,0xd4,0x01,0x04,0x00,0x00 # W32: v_cmp_lt_f16_e64 s10, s1, s2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x04,0x00,0x00] @@ -2385,6 +2389,19 @@ 0x7c,0x83,0x01,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00 # GFX12: v_cmp_lt_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x01,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00] +0x0a,0x08,0x01,0xd4,0x01,0x05,0x02,0x00 +# W32-REAL16: v_cmp_lt_f16_e64 s10, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x01,0xd4,0x01,0x05,0x02,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] +# W64-REAL16: v_cmp_lt_f16_e64 s[10:11], v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x01,0xd4,0x01,0x05,0x02,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00] + +0x0a,0x10,0x01,0xd4,0xff,0xff,0x03,0x00 +# W32-REAL16: v_cmp_lt_f16_e64 s10, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x01,0xd4,0xff,0xff,0x03,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] +# W64-REAL16: v_cmp_lt_f16_e64 s[10:11], v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x01,0xd4,0xff,0xff,0x03,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x01,0xd4,0xff,0xff,0x03,0x00] + + 0x0a,0x00,0x11,0xd4,0x01,0x05,0x02,0x00 # W32: v_cmp_lt_f32_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x11,0xd4,0x01,0x05,0x02,0x00] # W64: v_cmp_lt_f32_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x11,0xd4,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt index 8c782471db224..487a71d59e273 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,W32-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,W32-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,W64-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff # W32: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] @@ -1660,63 +1660,106 @@ # GFX12: v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x15,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] 0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] 0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff -# W32: v_cmp_lt_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] -# W64: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s104, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x01,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] 0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01 -# W32: v_cmp_lt_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] -# W64: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +# W32-REAL16: v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +# W64-REAL16: v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x01,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] 0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13 -# W32: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] -# W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W32-REAL16: v_cmp_lt_f16_e64_dpp ttmp14, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] 0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30 -# GFX12: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W32-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W64-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] + +0x7a,0x0a,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13 +# W32-REAL16: v_cmp_lt_f16_e64_dpp ttmp14, -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x0a,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x0a,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x01,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] + +0x7c,0x93,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30 +# W32-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x93,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W64-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x93,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] 0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff # W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x11,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt index cb9f8f4799743..3fc6cbf4e3cd4 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,W32-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,W32-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,W64-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,W64-FAKE16 %s 0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 # W32: v_cmp_class_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] @@ -661,27 +661,52 @@ # GFX12: v_cmp_lg_f32_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x15,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] 0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x0a,0x00,0x01,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16_e64_dpp s10, v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16_e64_dpp s[10:11], v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s10, v1.l, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s10, v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[10:11], v1.l, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[10:11], v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05] 0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16_e64_dpp s104, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x01,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x01,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] 0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16_e64_dpp ttmp14, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] 0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00 -# GFX12: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W32-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +0x7a,0x0a,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05 +# W32-REAL16: v_cmp_lt_f16_e64_dpp ttmp14, -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x0a,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x0a,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x01,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +0x7c,0x93,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00 +# W32-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x93,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x93,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x01,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] 0x0a,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 # W32: v_cmp_lt_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x11,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt index 3054c5e04f7a8..3048b8553c7ec 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-FAKE16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0x01,0x05,0xfa,0x7c # W32: v_cmp_class_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c] @@ -2357,64 +2357,118 @@ # W64: v_cmp_lg_f64_e32 vcc, 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0x4b,0x7c,0x56,0x34,0x12,0xaf] 0x01,0x05,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x02,0x7c] 0x7f,0x05,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x02,0x7c] 0x01,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x02,0x7c] 0x69,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x02,0x7c] 0x6a,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x02,0x7c] 0x6b,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x02,0x7c] 0x7b,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x02,0x7c] 0x7d,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x02,0x7c] 0x7e,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x02,0x7c] 0x7f,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x02,0x7c] 0x7c,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x02,0x7c] 0xc1,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x02,0x7c] 0xf0,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x02,0x7c] 0xfd,0x04,0x02,0x7c -# W32: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] -# W64: v_cmp_lt_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x02,0x7c] 0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00 -# W32: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] -# W64: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x02,0x7c,0x0b,0xfe,0x00,0x00] + +0x81,0x05,0x02,0x7c +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x02,0x7c] + +0xff,0x05,0x02,0x7c +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0x02,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0x02,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x02,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x02,0x7c] + +0xfd,0x04,0x03,0x7c +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0x03,0x7c] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0x03,0x7c] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0x03,0x7c] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0x03,0x7c] + +0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00 +# W32-REAL16: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16_e32 vcc_lo, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16_e32 vcc, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0x03,0x7c,0x0b,0xfe,0x00,0x00] 0x01,0x05,0x22,0x7c # W32: v_cmp_lt_f32_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x22,0x7c] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt index 4541c669793ad..213a79fdc8ed4 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-FAKE16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff # W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff] @@ -1573,60 +1573,100 @@ # W64: v_cmp_lg_f32 vcc, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x2b,0x7c,0xff,0x6f,0xfd,0x30] 0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x40,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x41,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x01,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x11,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x21,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x50,0x01,0xff] 0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01 -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13 -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] -# W64: v_cmp_lt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x02,0x7c,0x01,0x60,0x01,0x13] 0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30 -# W32: v_cmp_lt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] -# W64: v_cmp_lt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] +# W64-REAL16: v_cmp_lt_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] +# W64-FAKE16: v_cmp_lt_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x02,0x7c,0x7f,0x6f,0xfd,0x30] + +0xfa,0x04,0x03,0x7c,0x81,0x60,0x01,0x13 +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x01,0x13] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x01,0x13] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x01,0x13] +# W64-FAKE16: v_cmp_lt_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x03,0x7c,0x81,0x60,0x01,0x13] + +0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xfd,0x30 +# W32-REAL16: v_cmp_lt_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xfd,0x30] +# W64-REAL16: v_cmp_lt_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xfd,0x30] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xfd,0x30] +# W64-FAKE16: v_cmp_lt_f16 vcc, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x03,0x7c,0xff,0x6f,0xfd,0x30] 0xfa,0x04,0x22,0x7c,0x01,0x1b,0x00,0xff # W32: v_cmp_lt_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x22,0x7c,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt index a060e97e0161b..ff3dc4a54c628 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32 -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-REAL16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W32,W32-FAKE16 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck %s --check-prefixes=W64,W64-FAKE16 0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05 # W32: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05] @@ -229,12 +229,29 @@ # W64: v_cmp_lg_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x2b,0x7c,0xff,0x00,0x00,0x00] 0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05 -# W32: v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] -# W64: v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x02,0x7c,0x01,0x77,0x39,0x05] 0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00 -# W32: v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] -# W64: v_cmp_lt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x02,0x7c,0x7f,0x00,0x00,0x00] + +0xe9,0x04,0x03,0x7c,0x81,0x77,0x39,0x05 +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] +# W64-REAL16: v_cmp_lt_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] +# W64-FAKE16: v_cmp_lt_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x03,0x7c,0x81,0x77,0x39,0x05] + +0xea,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00 +# W32-REAL16: v_cmp_lt_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] +# W64-REAL16: v_cmp_lt_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] +# W32-FAKE16: v_cmp_lt_f16 vcc_lo, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] +# W64-FAKE16: v_cmp_lt_f16 vcc, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x03,0x7c,0xff,0x00,0x00,0x00] + 0xe9,0x04,0x22,0x7c,0x01,0x77,0x39,0x05 # W32: v_cmp_lt_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x22,0x7c,0x01,0x77,0x39,0x05]