@@ -16,113 +16,113 @@ define void @f1(i64 %x) nounwind {
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; TR-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; TR-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
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; TR-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
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- ; TR-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
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- ; TR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
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- ; TR-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
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- ; TR-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
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+ ; TR-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
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+ ; TR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
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+ ; TR-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
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+ ; TR-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
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; TR-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
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; TR: [[BB7]]:
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; TR-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
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; TR-NEXT: ret void
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; TR: [[TRAP]]:
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- ; TR-NEXT: call void @llvm.trap() #[[ATTR2:[0-9]+]]
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- ; TR-NEXT: unreachable
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+ ; TR-NEXT: call void @llvm.trap() #[[ATTR2:[0-9]+]], !nosanitize [[META0]]
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+ ; TR-NEXT: unreachable, !nosanitize [[META0]]
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;
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; RT-LABEL: define void @f1(
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; RT-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; RT-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
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; RT-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
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- ; RT-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
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- ; RT-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
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- ; RT-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
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- ; RT-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
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+ ; RT-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
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+ ; RT-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
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+ ; RT-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
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+ ; RT-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
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; RT-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
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; RT: [[BB7]]:
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; RT-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
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; RT-NEXT: ret void
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; RT: [[TRAP]]:
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- ; RT-NEXT: call void @__ubsan_handle_local_out_of_bounds() #[[ATTR0]]
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- ; RT-NEXT: br label %[[BB7]]
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+ ; RT-NEXT: call void @__ubsan_handle_local_out_of_bounds() #[[ATTR0]], !nosanitize [[META0]]
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+ ; RT-NEXT: br label %[[BB7]], !nosanitize [[META0]]
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;
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; TR-NOMERGE-LABEL: define void @f1(
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; TR-NOMERGE-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; TR-NOMERGE-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
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; TR-NOMERGE-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
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- ; TR-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
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- ; TR-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
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- ; TR-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
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- ; TR-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
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+ ; TR-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
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+ ; TR-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
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+ ; TR-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
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+ ; TR-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
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; TR-NOMERGE-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
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; TR-NOMERGE: [[BB7]]:
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; TR-NOMERGE-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
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; TR-NOMERGE-NEXT: ret void
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; TR-NOMERGE: [[TRAP]]:
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- ; TR-NOMERGE-NEXT: call void @llvm.ubsantrap(i8 3) #[[ATTR2:[0-9]+]]
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- ; TR-NOMERGE-NEXT: unreachable
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+ ; TR-NOMERGE-NEXT: call void @llvm.ubsantrap(i8 3) #[[ATTR2:[0-9]+]], !nosanitize [[META0]]
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+ ; TR-NOMERGE-NEXT: unreachable, !nosanitize [[META0]]
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;
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; RT-NOMERGE-LABEL: define void @f1(
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; RT-NOMERGE-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; RT-NOMERGE-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
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; RT-NOMERGE-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
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- ; RT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
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- ; RT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
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- ; RT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
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- ; RT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
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+ ; RT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
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+ ; RT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
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+ ; RT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
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+ ; RT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
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; RT-NOMERGE-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
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; RT-NOMERGE: [[BB7]]:
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; RT-NOMERGE-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
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; RT-NOMERGE-NEXT: ret void
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; RT-NOMERGE: [[TRAP]]:
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- ; RT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds() #[[ATTR1:[0-9]+]]
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- ; RT-NOMERGE-NEXT: br label %[[BB7]]
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+ ; RT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds() #[[ATTR1:[0-9]+]], !nosanitize [[META0]]
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+ ; RT-NOMERGE-NEXT: br label %[[BB7]], !nosanitize [[META0]]
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;
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; RTABORT-NOMERGE-LABEL: define void @f1(
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; RTABORT-NOMERGE-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; RTABORT-NOMERGE-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
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; RTABORT-NOMERGE-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
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- ; RTABORT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
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- ; RTABORT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
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- ; RTABORT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
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- ; RTABORT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
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+ ; RTABORT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
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+ ; RTABORT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
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+ ; RTABORT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
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+ ; RTABORT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
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; RTABORT-NOMERGE-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
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; RTABORT-NOMERGE: [[BB7]]:
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; RTABORT-NOMERGE-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
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; RTABORT-NOMERGE-NEXT: ret void
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; RTABORT-NOMERGE: [[TRAP]]:
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- ; RTABORT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_abort() #[[ATTR2:[0-9]+]]
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- ; RTABORT-NOMERGE-NEXT: unreachable
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+ ; RTABORT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_abort() #[[ATTR2:[0-9]+]], !nosanitize [[META0]]
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+ ; RTABORT-NOMERGE-NEXT: unreachable, !nosanitize [[META0]]
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;
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; MINRT-NOMERGE-LABEL: define void @f1(
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; MINRT-NOMERGE-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; MINRT-NOMERGE-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
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; MINRT-NOMERGE-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
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- ; MINRT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
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- ; MINRT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
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- ; MINRT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
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- ; MINRT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
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+ ; MINRT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
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+ ; MINRT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
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+ ; MINRT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
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+ ; MINRT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
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; MINRT-NOMERGE-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
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; MINRT-NOMERGE: [[BB7]]:
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; MINRT-NOMERGE-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
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; MINRT-NOMERGE-NEXT: ret void
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; MINRT-NOMERGE: [[TRAP]]:
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- ; MINRT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_minimal() #[[ATTR1:[0-9]+]]
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- ; MINRT-NOMERGE-NEXT: br label %[[BB7]]
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+ ; MINRT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_minimal() #[[ATTR1:[0-9]+]], !nosanitize [[META0]]
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+ ; MINRT-NOMERGE-NEXT: br label %[[BB7]], !nosanitize [[META0]]
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;
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; MINRTABORT-NOMERGE-LABEL: define void @f1(
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; MINRTABORT-NOMERGE-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; MINRTABORT-NOMERGE-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
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; MINRTABORT-NOMERGE-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
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- ; MINRTABORT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
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- ; MINRTABORT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
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- ; MINRTABORT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
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- ; MINRTABORT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
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+ ; MINRTABORT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
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+ ; MINRTABORT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
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+ ; MINRTABORT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
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+ ; MINRTABORT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
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; MINRTABORT-NOMERGE-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
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; MINRTABORT-NOMERGE: [[BB7]]:
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; MINRTABORT-NOMERGE-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
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; MINRTABORT-NOMERGE-NEXT: ret void
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; MINRTABORT-NOMERGE: [[TRAP]]:
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- ; MINRTABORT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_minimal_abort() #[[ATTR2:[0-9]+]]
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- ; MINRTABORT-NOMERGE-NEXT: unreachable
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+ ; MINRTABORT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_minimal_abort() #[[ATTR2:[0-9]+]], !nosanitize [[META0]]
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+ ; MINRTABORT-NOMERGE-NEXT: unreachable, !nosanitize [[META0]]
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;
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%1 = alloca i128 , i64 %x
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%3 = load i128 , ptr %1 , align 4
@@ -154,3 +154,17 @@ define void @f1(i64 %x) nounwind {
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; MINRTABORT-NOMERGE: attributes #[[ATTR1:[0-9]+]] = { noreturn nounwind }
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; MINRTABORT-NOMERGE: attributes #[[ATTR2]] = { nomerge noreturn nounwind }
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;.
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+ ; TR: [[META0]] = !{}
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+ ;.
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+ ; RT: [[META0]] = !{}
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+ ;.
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+ ; TR-NOMERGE: [[META0]] = !{}
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+ ;.
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+ ; RT-NOMERGE: [[META0]] = !{}
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+ ;.
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+ ; RTABORT-NOMERGE: [[META0]] = !{}
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+ ;.
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+ ; MINRT-NOMERGE: [[META0]] = !{}
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+ ;.
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+ ; MINRTABORT-NOMERGE: [[META0]] = !{}
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+ ;.
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