- Revision numbers following the ArchC release
- Instructions with cycles annotations
- Two new .ac files to use with MPSoCBench (block and nonblock)
- sparc_isa.cpp using the reserved work DATA_PORT to data request. See the commit message.
- Interrupt handler support. It is inactive in standalone simulator.
- New PowerSC tables
- Revision numbers following the ArchC release
- PowerSC support with power tables
- Added id register for core identification
- ArchC 2.2 compliant
- Added binary utilities support files
- ArchC 2.0 compliant
- Fixed an annoying bug which caused a segfault on the fft program (MiBench)
- Added license headers
- Model compliant with ArchC 2.0beta1
- Fixed 'unimplemented' instruction format and assembly syntax
- Fixed bug in mulscc_reg and mulscc_imm instructions (condition codes)
- npc initialization depends on ac_pc, so program can start at arbitrary address
- Included assembly language syntax information
- Fix bug in instruction MULSCC (used only for V7 multiplication)
- New REGS register bank holds the current register window from RB
- Use ArchC support for debug messages: ac_debug_model.H
- Use operator[] syntax to read register banks, which is faster
- Included optimization instruction methods for compiled simulation
- Separate nop instruction from sethi to optimize simulation
- Included file for GDB integration
- Model passed selected Mediabench and Mibench applications