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base repository: pheaver/netlist-verilog
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Commits on Feb 6, 2011

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Commits on May 8, 2011

  1. Removing the ugly trailing _ram after every memdecl.

    andygill authored and Andrew Gill committed May 8, 2011
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  2. Adding MemAssign and MemDecl initializations.

    Andrew Gill committed May 8, 2011
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  3. And fixing a bad merge with the Async recoding.

    Andrew Gill committed May 8, 2011
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  4. Merge remote-tracking branch 'csdl/master'

    Conflicts:
    	netlist-to-vhdl/Language/Netlist/GenVHDL.hs
    	netlist/Language/Netlist/AST.hs
    	netlist/Language/Netlist/Examples.hs
    Andrew Gill committed May 8, 2011
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  5. fix bad merge from CSDL repo.

    Andrew Gill committed May 8, 2011
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  6. Fixing (again, finally) the merge problems.

    Andrew Gill committed May 8, 2011
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Commits on Oct 22, 2011

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Commits on Oct 24, 2011

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Commits on Oct 28, 2011

  1. Adding myself as maintainer.

    andygill committed Oct 28, 2011
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  2. Fixing netlist depends.

    andygill committed Oct 28, 2011
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Commits on Jun 28, 2013

  1. 1. GenVerilog.hs: Temporarily removed support for ProcessDecl

    2. netlist-to-verilog/netlist-to-verilog.cabal: Changed version numbers of dependencies
    3. Expression.hs: Added the (Show a) constraint as it is no longer (ghc7.6.3) implied by (Integral a)
    anshulmalvi committed Jun 28, 2013
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Commits on Aug 19, 2013

  1. Added "Show" constraint (no longer implied by Num).

    Neil Sculthorpe committed Aug 19, 2013
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Commits on Feb 8, 2014

  1. In cases where VHDL syntax requires semicolons *after* lines, not *be…

    …tween* them, don't emit a semicolon for empty lists
    gergoerdi committed Feb 8, 2014
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Commits on Feb 23, 2014

  1. Merge pull request #3 from gergoerdi/master

    Fix for pretty-printing of Modules with no internal signals
    andygill committed Feb 23, 2014
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  2. merging Integral fix

    andygill committed Feb 23, 2014
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  5. Adding ~ to ignore

    andygill committed Feb 23, 2014
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Commits on Oct 22, 2014

  1. Restore ProcessDecl handling

    conal committed Oct 22, 2014
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Commits on Oct 24, 2014

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  2. Register initialization

    conal committed Oct 24, 2014
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  3. bump version to 0.1.2

    conal committed Oct 24, 2014
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Commits on Feb 8, 2015

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Commits on Feb 16, 2015

  1. Travis integration, fix GHC 7.10 warnings

    RyanGlScott committed Feb 16, 2015
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  2. Detailed Travis build output

    RyanGlScott committed Feb 16, 2015
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Commits on Apr 16, 2015

  1. Update .travis.yml

    RyanGlScott committed Apr 16, 2015
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Commits on Jul 29, 2015

  1. Use GHC 7.10.2

    RyanGlScott committed Jul 29, 2015
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Commits on Aug 5, 2017

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  3. reinstated a mk_decl case

    conal committed Aug 5, 2017
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Commits on Aug 22, 2017

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  2. Merge pull request #4 from capn-freako/master

    Added support for Verilog floating point type.
    conal authored Aug 22, 2017
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Commits on Apr 6, 2018

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Commits on Aug 3, 2018

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1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -1,2 +1,3 @@
dist/
package.conf.d/
*~
32 changes: 32 additions & 0 deletions .travis.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
# NB: don't set `language: haskell` here

env:
- CABALVER=1.18 GHCVER=7.0.4
- CABALVER=1.18 GHCVER=7.2.2
- CABALVER=1.18 GHCVER=7.4.2
- CABALVER=1.18 GHCVER=7.6.3
- CABALVER=1.18 GHCVER=7.8.4
- CABALVER=1.22 GHCVER=7.10.2
- CABALVER=head GHCVER=head

matrix:
allow_failures:
- env: CABALVER=head GHCVER=head

before_install:
- travis_retry sudo add-apt-repository -y ppa:hvr/ghc
- travis_retry sudo apt-get update
- travis_retry sudo apt-get install cabal-install-$CABALVER ghc-$GHCVER
- export PATH=/opt/ghc/$GHCVER/bin:/opt/cabal/$CABALVER/bin:$PATH

install:
- cabal --version
- echo "$(ghc --version) [$(ghc --print-project-git-commit-id 2> /dev/null || echo '?')]"
- travis_retry cabal update
- cabal install netlist/ verilog/ -j --only-dependencies

script:
- ( cd netlist/ ; cabal configure ; cabal build ; cabal install ; cabal check ; cabal sdist )
- ( cd verilog/ ; cabal configure ; cabal build ; cabal install ; cabal check ; cabal sdist )
- ( cd netlist-to-vhdl; cabal install -j --only-dependencies; cabal configure ; cabal build ; cabal check ; cabal sdist )
- ( cd netlist-to-verilog; cabal install -j --only-dependencies; cabal configure ; cabal build ; cabal check ; cabal sdist )
45 changes: 37 additions & 8 deletions netlist-to-verilog/Language/Netlist/GenVerilog.hs
Original file line number Diff line number Diff line change
@@ -19,6 +19,8 @@
--------------------------------------------------------------------------------
{-# LANGUAGE ViewPatterns #-}

{-# OPTIONS_GHC -Wall #-}

-- TODO: endianness - currently we're hardcoded to little endian verilog

module Language.Netlist.GenVerilog ( mk_module
@@ -65,12 +67,16 @@ mk_decl (NetDecl x mb_range mb_expr)
mk_decl (NetAssign x expr)
= [V.AssignItem Nothing Nothing [mkAssign x expr]]

mk_decl (MemDecl x mb_range1 mb_range2)
mk_decl (MemDecl x mb_range1 mb_range2 startMb)
= [V.RegDeclItem (V.RegDecl V.Reg_reg (fmap mk_range mb_range2)
[case mb_range1 of
Nothing -> V.RegVar (mk_ident x) Nothing
Nothing -> V.RegVar (mk_ident x) (fmap mk_exprs startMb)
Just r -> V.MemVar (mk_ident x) (mk_range r)
])]
where
mk_exprs :: [Expr] -> V.Expression
mk_exprs [e] = mk_expr e
mk_exprs es = mk_expr (ExprConcat es)

mk_decl (InstDecl mod_name inst_name params inputs outputs)
= [V.InstanceItem (V.Instance (mk_ident mod_name) v_params [inst])]
@@ -90,23 +96,27 @@ mk_decl (CommentDecl str)
mk_decl (ProcessDecl (Event (mk_expr -> clk) edge) Nothing stmt)
= [V.AlwaysItem (V.EventControlStmt e (Just s))]
where
e = V.EventControlExpr event
s = V.IfStmt cond (Just (mk_stmt stmt)) Nothing

(event, cond) = edge_helper edge clk
e = V.EventControlExpr event
s = mk_stmt stmt
(event, _) = edge_helper edge clk
-- conal: simplified from below, removing redundant (I think) conditional.
-- s = V.IfStmt cond (Just (mk_stmt stmt)) Nothing
-- (event, cond) = edge_helper edge clk

mk_decl (ProcessDecl (Event (mk_expr -> clk) clk_edge)
(Just (Event (mk_expr -> reset) reset_edge, reset_stmt)) stmt)
= [V.AlwaysItem (V.EventControlStmt e (Just s1))]
where
e = V.EventControlExpr (V.EventOr clk_event reset_event)

s1 = V.IfStmt reset_cond (Just (mk_stmt reset_stmt)) (Just s2)
s2 = V.IfStmt clk_cond (Just (mk_stmt stmt)) Nothing

(clk_event, clk_cond) = edge_helper clk_edge clk
(reset_event, reset_cond) = edge_helper reset_edge reset

mk_decl decl =
error ("Language.Netlist.GenVerilog.mk_decl: unexpected decl "
++ show decl)

edge_helper :: Edge -> V.Expression -> (V.EventExpr, V.Expression)
edge_helper PosEdge x = (V.EventPosedge x, x)
edge_helper NegEdge x = (V.EventNegedge x, V.ExprUnary V.UBang x)
@@ -137,6 +147,19 @@ mk_stmt (FunCallStmt x es)
= error ("FunCallStmt " ++ x)

mk_lit :: Maybe Size -> ExprLit -> V.Number
-- | A real number: sign, integral integral, fractional part, exponent sign,
-- and exponent value
-- | RealNum (Maybe Sign) String (Maybe String) (Maybe (Maybe Sign, String))
-- data Sign
-- = Pos | Neg
-- mk_lit mb_sz (ExprFloat x) = V.RealNum sn int frac es ev
mk_lit mb_sz (ExprFloat x) = V.RealNum sn (show int) frac Nothing
where sn | x < 0.0 = Just V.Neg
| otherwise = Nothing
int | x < 0.0 = abs $ floor x + 1
| otherwise = floor x
frac = Just . tail . tail . show $ abs x - (fromIntegral int)

mk_lit mb_sz lit
= V.IntNum Nothing (fmap show mb_sz) mb_base str
-- Note that this does not truncate 'str' if its length is more than the size.
@@ -153,6 +176,7 @@ mk_lit mb_sz lit
Nothing -> (show x, Nothing)
ExprBit b -> ([bit_char b], Nothing)
ExprBitVector bs -> (map bit_char bs, Just V.BinBase)
_ -> error $ "This should never happen!" ++ (show lit)

bit_char :: Bit -> Char
bit_char T = '1'
@@ -240,4 +264,9 @@ binary_op ShiftRight = V.ShiftRight
binary_op RotateLeft = error "GenVerilog: no left-rotate operator in Verilog"
binary_op RotateRight = error "GenVerilog: no right-rotate operator in Verilog"

binary_op op =
error ("Language.Netlist.GenVerilog.binary_op: unexpected op "
++ show op)


-- -----------------------------------------------------------------------------
3 changes: 3 additions & 0 deletions netlist-to-verilog/README.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
# netlist-to-verilog

Convert a Netlist AST to a Verilog AST
31 changes: 16 additions & 15 deletions netlist-to-verilog/netlist-to-verilog.cabal
Original file line number Diff line number Diff line change
@@ -1,17 +1,18 @@
name: netlist-to-verilog
version: 0.1
synopsis: Convert a Netlist AST to a Verilog AST
description: Convert a Netlist AST to a Verilog AST
category: Language
license: BSD3
license-file: LICENSE
copyright: Copyright (c) 2010 Signali Corp.
Copyright (c) 2010 Philip Weaver
author: Philip Weaver
maintainer: philip.weaver@gmail.com
package-url: git://github.com/pheaver/netlist-verilog.git
build-type: Simple
cabal-version: >=1.6
name: netlist-to-verilog
version: 0.1.2
synopsis: Convert a Netlist AST to a Verilog AST
description: Convert a Netlist AST to a Verilog AST
category: Language
license: BSD3
license-file: LICENSE
copyright: Copyright (c) 2010 Signali Corp.
Copyright (c) 2010 Philip Weaver
author: Philip Weaver
maintainer: philip.weaver@gmail.com
package-url: git://github.com/pheaver/netlist-verilog.git
build-type: Simple
cabal-version: >=1.6
extra-source-files: README.md

flag base4
Description: Compile using base-4 instead of base-3
@@ -22,7 +23,7 @@ Library

exposed-modules: Language.Netlist.GenVerilog

build-depends: netlist == 0.2, verilog == 0.2
build-depends: netlist >= 0.2, verilog == 0.2

if flag(base4)
build-depends: base == 4.*
47 changes: 27 additions & 20 deletions netlist-to-vhdl/Language/Netlist/GenVHDL.hs
Original file line number Diff line number Diff line change
@@ -11,12 +11,16 @@
-- Translates a Netlist AST ('Language.Netlist.AST') to VHDL.
--------------------------------------------------------------------------------

{-# LANGUAGE CPP #-}
module Language.Netlist.GenVHDL(genVHDL) where

import Language.Netlist.AST

#if MIN_VERSION_base(4,11,0)
import Prelude hiding ((<>))
#endif
import Text.PrettyPrint
import Data.Maybe(catMaybes)
import Data.Maybe(catMaybes, mapMaybe)


-- | Generate a 'Language.Netlist.AST.Module' as a VHDL file . The ['String'] argument
@@ -30,12 +34,12 @@ genVHDL m others = render vhdl ++ "\n"

imports :: [String] -> Doc
imports others = vcat
[ text "library IEEE" <> semi
[ text "library IEEE" <> semi
, text "use IEEE.STD_LOGIC_1164.ALL" <> semi
, text "use IEEE.NUMERIC_STD.ALL" <> semi
] $$ vcat [
] $$ vcat [
text ("use " ++ other) <> semi
| other <- others
| other <- others
]


@@ -56,36 +60,37 @@ architecture m = text "architecture" <+> text "str" <+> text "of" <+> text (mod
text "end" <+> text "architecture" <+> text "str" <> semi

decls :: [Decl] -> Doc
decls [] = empty
decls ds = (vcat $ punctuate semi $ catMaybes $ map decl ds) <> semi
decls = vcat . map (<> semi) . mapMaybe decl

decl :: Decl -> Maybe Doc
decl (NetDecl i r Nothing) = Just $
text "signal" <+> text i <+> colon <+> slv_type r

decl (NetDecl i r (Just init)) = Just $
text "signal" <+> text i <+> colon <+> slv_type r <+> text ":=" <+> expr init
decl (NetDecl i r (Just init')) = Just $
text "signal" <+> text i <+> colon <+> slv_type r <+> text ":=" <+> expr init'

decl (MemDecl i Nothing dsize) = Just $
decl (MemDecl i Nothing dsize Nothing) = Just $
text "signal" <+> text i <+> colon <+> slv_type dsize

decl (MemDecl i (Just asize) dsize) = Just $
decl (MemDecl i (Just asize) dsize def) = Just $
text "type" <+> mtype <+> text "is" <+>
text "array" <+> range asize <+> text "of" <+> slv_type dsize <> semi $$
text "signal" <+> text i <> text "_ram" <+> colon <+> mtype
where mtype = text i <> text "_memory_type"
text "signal" <+> text i <+> colon <+> mtype <> def_txt
where mtype = text i <> text "_type"
def_txt = case def of
Nothing -> empty
Just [xs] -> empty <+> text ":=" <+> parens (text "0 =>" <+> expr xs)
Just xs -> empty <+> text ":=" <+> parens (vcat $ punctuate comma (map expr xs))

decl _d = Nothing

insts :: [Decl] -> Doc
insts [] = empty
insts is = case catMaybes $ zipWith inst gensyms is of
[] -> empty
is' -> (vcat $ punctuate semi is') <> semi
insts = vcat . map (<> semi) . catMaybes . zipWith inst gensyms
where gensyms = ["proc" ++ show i | i <- [(0::Integer)..]]

inst :: String -> Decl -> Maybe Doc
inst _ (NetAssign i e) = Just $ text i <+> text "<=" <+> expr e
inst _ (MemAssign i idx e) = Just $ text i <> parens (expr idx) <+> text "<=" <+> expr e

inst gensym (ProcessDecl (Event clk edge) Nothing s) = Just $
text gensym <+> colon <+> text "process" <> senlist <+> text "is" $$
@@ -120,8 +125,8 @@ inst gensym (ProcessDecl (Event clk clk_edge)
NegEdge -> expr reset <+> text "= '0'"


inst _ (InstDecl nm inst gens ins outs) = Just $
text inst <+> colon <+> text "entity" <+> text nm $$
inst _ (InstDecl nm inst' gens ins outs) = Just $
text inst' <+> colon <+> text "entity" <+> text nm $$
gs $$
ps
where
@@ -146,7 +151,7 @@ inst gensym (InitProcessDecl s) = Just $

-- TODO: get multline working
inst _ (CommentDecl msg) = Just $
(vcat [ text "--" <+> text m | m <- lines msg ])
(vcat [ text "--" <+> text m | m <- lines msg ])

inst _ _d = Nothing

@@ -219,7 +224,7 @@ expr (ExprCase _ [] Nothing) = error "VHDL does not support non-defaulted ExprCa
expr (ExprCase _ [] (Just e)) = expr e
expr (ExprCase e (([],_):alts) def) = expr (ExprCase e alts def)
expr (ExprCase e ((p:ps,alt):alts) def) =
expr (ExprCond (ExprBinary Equals e p) alt (ExprCase e ((ps,alt):alts) def))
expr (ExprCond (ExprBinary Equals e p) alt (ExprCase e ((ps,alt):alts) def))
expr x = text (show x)


@@ -270,6 +275,8 @@ binOp ShiftLeft = "sll"
binOp ShiftRight = "srl"
binOp RotateLeft = "rol"
binOp RotateRight = "ror"
binOp ShiftLeftArith = "sla"
binOp ShiftRightArith = "sra"

slv_type :: Maybe Range -> Doc
slv_type Nothing = text "std_logic"
3 changes: 3 additions & 0 deletions netlist-to-vhdl/README.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
# netlist-to-vhdl [![Hackage version](https://img.shields.io/hackage/v/netlist-to-vhdl.svg?style=flat)](http://hackage.haskell.org/package/netlist-to-vhdl)

Convert a Netlist AST to VHDL
38 changes: 24 additions & 14 deletions netlist-to-vhdl/netlist-to-vhdl.cabal
Original file line number Diff line number Diff line change
@@ -1,16 +1,17 @@
name: netlist-to-vhdl
version: 0.2
synopsis: Convert a Netlist AST to VHDL
description: Convert a Netlist AST to VHDL
category: Language
license: BSD3
license-file: LICENSE
copyright: Copyright (c) 2010 University of Kansas
author: Garrin Kimmell
maintainer: garrin.kimmell@gmail.com
package-url: git://github.com/pheaver/netlist-verilog.git
build-type: Simple
cabal-version: >=1.6
name: netlist-to-vhdl
version: 0.3.3
synopsis: Convert a Netlist AST to VHDL
description: Convert a Netlist AST to VHDL
category: Language
license: BSD3
license-file: LICENSE
copyright: Copyright (c) 2010 University of Kansas
author: Garrin Kimmell
maintainer: garrin.kimmell@gmail.com
package-url: git://github.com/ku-fpg/netlist.git
build-type: Simple
cabal-version: >=1.6
extra-source-files: README.md

flag base4
Description: Compile using base-4 instead of base-3
@@ -21,9 +22,18 @@ Library

exposed-modules: Language.Netlist.GenVHDL

build-depends: netlist == 0.2, pretty >= 1.0
build-depends: netlist >= 0.3.1 && < 0.4, pretty >= 1.0

if flag(base4)
build-depends: base == 4.*
else
build-depends: base == 3.*

source-repository head
type: git
location: git://github.com/ku-fpg/netlist.git

source-repository this
type: git
location: git://github.com/ku-fpg/netlist.git
tag: netlist-to-vhdl-0.3.2
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