DOCSIS 4.0: BCM33940/BCM33941 #80
Description
Hi, DOCSIS 4.0 is here. Broadcom's DOCSIS 4.0 chip is the BCM33940/BCM33941. The associated R-PHY chip appears to be BCM3162/BCM3163. I found a kernel patch referencing these chips: https://lore.kernel.org/all/[email protected]/
BCM3394x is a quad-core ARM cortex a53 chip, but Broadcom calls it a b53 core. It has a separate co-processor called "SMC", probably "Secure Monitor Coprocessor" or something. The unique part about this SoC is the entire flash appears encrypted, including the boot loaders.
From what I can tell, the bootROM contains the logic and keys to decrypt and verify each flash partition, and there are a lot:
flash-smcnvo LUN 0 124KB
flash-smcnvb LUN 1 124KB
flash-bolto LUN 2 1MB
flash-boltb LUN 3 1MB
flash-kernelo LUN 4 16MB
flash-kernelb LUN 5 16MB
flash-rgo LUN 6 1023MB
flash-rgb LUN 7 1023MB
flash-cmblo LUN 8 1MB
flash-cmblb LUN 9 1MB
flash-cmo LUN 10 20MB
flash-cmb LUN 11 20MB
flash-nvramo LUN 12 124KB
flash-nvramb LUN 13 124KB
flash-devtreeo LUN 14 512KB
flash-devtreeb LUN 15 512KB
flash-rgnonvolo LUN 16 39MB
flash-rgnonvolb LUN 17 39MB
flash-rdknvramo LUN 18 99MB
flash-rdknvramb LUN 19 99MB
flash-cmnvpo LUN 20 1MB
flash-cmnvpb LUN 21 1MB
flash-cmnvdo LUN 22 1MB
flash-cmnvdb LUN 23 1MB
flash-smcblo LUN 24 256KB
flash-smcblb LUN 25 256KB
flash-smcoso LUN 26 1MB
flash-smcosb LUN 27 1MB
flash-gfapo LUN 28 1MB
flash-gfapb LUN 29 1MB
flash-macadro LUN 30 124KB
flash-macadrb LUN 31 124KB
flash-reservedo LUN 32 1MB
flash-reservedb LUN 33 1MB
flash-asfo LUN 34 8MB
flash-asfb LUN 35 8MB
flash-custcfgpo LUN 36 128KB
flash-custcfgpb LUN 37 128KB
flash-stao LUN 38 256MB
flash-stab LUN 39 256MB
flash-debugo LUN 40 3MB
flash-ramlogo LUN 41 4MB
flash-amso LUN 42 2MB
flash-amsb LUN 43 2MB
flash-atao LUN 44 8MB
flash-atab LUN 45 8MB
flash-bp3lico LUN 46 31MB
flash-bp3licb LUN 47 31MB
flash-smcnvexto LUN 48 252KB
flash-smcnvextb LUN 49 252KB
flash-custcfgdo LUN 50 256KB
flash-custcfgdb LUN 51 256KB
flash-customo LUN 52 2GB
flash-customb LUN 53 2GB
The partitions are also exposed to the kernel via a Logical Unit Number (LUN) rather than directly as an eMMC storage device. The kernel can see all the partitions, but many it cannot ready (SMC*) and many are encrypted even when booted.
BOLT is still used as the application processor's boot loader. Here's the soc_base device tree:
SoC Base Device Tree
/dts-v1/;
/ {
#address-cells = <0x02>;
#size-cells = <0x02>;
interrupt-parent = <0x01>;
compatible = "brcm,soc_base", "brcm,brcmcm", "brcm,brcmstb";
platform-match {
layer = <0x00>;
match = "!((e & !f) | g | h | i | j)";
e {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0x316200>;
};
f {
type = "env";
env-var = "CMTS_TYPE";
};
g {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf5790000>;
};
h {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf9fc0000>;
};
i {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf6510000>;
};
j {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf2b00000>;
};
};
chosen {
bootargs = "root=/dev/flash-rgo earlycon debug bhpa=0@0 nr_cpus=1";
stdout-path = "/dbg-uarta:115200";
phandle = <0x1a>;
};
reserved-memory {
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
phandle = <0x1b>;
reserved-nodma@0 {
reg = <0x00 0x00 0x00 0x1000>;
};
NWMBOX {
compatible = "arm,scmi-shmem";
phandle = <0x04>;
};
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@0 {
device_type = "cpu";
enable-method = "brcm,brahma-b53";
compatible = "brcm,brahma-b53", "arm,cortex-a53";
reg = <0x00>;
next-level-cache = <0x02>;
clocks = <0x03 0x00>;
clock-names = "cpu";
};
cpu@1 {
device_type = "cpu";
enable-method = "brcm,brahma-b53";
compatible = "brcm,brahma-b53", "arm,cortex-a53";
reg = <0x01>;
next-level-cache = <0x02>;
clocks = <0x03 0x00>;
clock-names = "cpu";
};
cpu@2 {
device_type = "cpu";
enable-method = "brcm,brahma-b53";
compatible = "brcm,brahma-b53", "arm,cortex-a53";
reg = <0x02>;
next-level-cache = <0x02>;
clocks = <0x03 0x00>;
clock-names = "cpu";
};
cpu@3 {
device_type = "cpu";
enable-method = "brcm,brahma-b53";
compatible = "brcm,brahma-b53", "arm,cortex-a53";
reg = <0x03>;
next-level-cache = <0x02>;
clocks = <0x03 0x00>;
clock-names = "cpu";
};
cache {
compatible = "cache";
phandle = <0x02>;
};
};
psci {
compatible = "arm,psci-0.2", "arm,psci";
method = "smc";
cpu_suspend = <0xc4000001>;
cpu_off = <0x84000002>;
cpu_on = <0xc4000003>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <0x01>;
interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0a 0xff08>;
clock-frequency = <0x19bfcc0>;
arm,cpu-registers-not-fw-configured;
always-on;
};
pmu {
compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3", "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
interrupt-parent = <0x01>;
interrupts = <0x00 0x09 0xf04 0x00 0x0a 0xf04 0x00 0x0b 0xf04 0x00 0x0c 0xf04>;
interrupt-names = "cpu_pmuirq_0", "cpu_pmuirq_1", "cpu_pmuirq_2", "cpu_pmuirq_3";
};
brcm_bogus_clk {
#clock-cells = <0x01>;
compatible = "fixed-clock";
clock-frequency = <0xbc614e>;
phandle = <0x03>;
};
brcm-scmi-mailbox0 {
#mbox-cells = <0x01>;
compatible = "brcm,brcmstb-mbox";
status = "disabled";
phandle = <0x1c>;
};
power {
compatible = "brcm,brcm-pwr-rpc";
reg = <0x00 0xd1240100 0x00 0x80 0x00 0xd1240000 0x00 0xb8>;
interrupts = <0x00 0xc5 0x04>;
interrupt-names = "cpucomm_1_toB53_irq";
mbox-irq-read-mask = <0x01>;
boot-state = "ac";
phandle = <0x1d>;
};
ba-rpc {
compatible = "brcm,brcm-ba-rpc";
rg-batt-mode = "cpu-on";
phandle = <0x1e>;
};
brcm-scmi0 {
compatible = "arm,scmi-smc";
shmem = <0x04>;
arm,smc-id = <0x83000400>;
interrupt-names = "a2p";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x1f>;
protocol@13 {
reg = <0x13>;
#clock-cells = <0x01>;
phandle = <0x20>;
};
protocol@14 {
reg = <0x14>;
#clock-cells = <0x01>;
phandle = <0x21>;
};
protocol@15 {
reg = <0x15>;
#sensor-cells = <0x01>;
#thermal-sensor-cells = <0x01>;
phandle = <0x22>;
};
protocol@80 {
reg = <0x80>;
#clock-cells = <0x01>;
phandle = <0x23>;
};
};
gic-intc {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <0x03>;
reg = <0x00 0xd0101000 0x00 0x1000 0x00 0xd0102000 0x00 0x2000>;
reg-names = "dist", "cpu";
phandle = <0x01>;
};
dbg-uarta {
compatible = "ns16550a";
reg = <0x00 0xd121c000 0x00 0x20>;
reg-shift = <0x02>;
reg-io-width = <0x04>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x1a 0x04>;
interrupt-names = "upg_uart_dbg0";
clock-frequency = <0x4d3f640>;
fifo-size = <0x20>;
auto-flow-control;
phandle = <0x24>;
};
uarta {
compatible = "ns16550a";
reg = <0x00 0xd1219000 0x00 0x20>;
reg-shift = <0x02>;
reg-io-width = <0x04>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x2c 0x04>;
interrupt-names = "upg_uart_0";
clock-frequency = <0x4d3f640>;
fifo-size = <0x20>;
auto-flow-control;
phandle = <0x25>;
};
uartd {
compatible = "ns16550a";
reg = <0x00 0xd121a200 0x00 0x20>;
reg-shift = <0x02>;
reg-io-width = <0x04>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x2f 0x04>;
interrupt-names = "upg_uart_3";
clock-frequency = <0x4d3f640>;
fifo-size = <0x20>;
auto-flow-control;
phandle = <0x26>;
};
upg-intc {
#interrupt-cells = <0x01>;
compatible = "brcm,bcm7271-l2-intc";
reg = <0x00 0xd1213980 0x00 0x10>;
interrupt-controller;
interrupt-parent = <0x01>;
interrupts = <0x00 0x1c 0x04>;
interrupt-names = "upg_main";
phandle = <0x08>;
};
i2c-a {
clock-frequency = <0xc350>;
compatible = "brcm,brcmper-i2c";
reg = <0x00 0xd1213100 0x00 0x58>;
interrupt-parent = <0x05>;
interrupts = <0x00>;
interrupt-names = "iica";
phandle = <0x27>;
};
i2c-d {
clock-frequency = <0xc350>;
compatible = "brcm,brcmper-i2c";
reg = <0x00 0xd1213280 0x00 0x58>;
interrupt-parent = <0x05>;
interrupts = <0x03>;
interrupt-names = "iicd";
phandle = <0x28>;
};
upg-bsc-intc {
#interrupt-cells = <0x01>;
compatible = "brcm,bcm7271-l2-intc";
reg = <0x00 0xd1213500 0x00 0x10>;
interrupt-controller;
interrupt-parent = <0x01>;
interrupts = <0x00 0x20 0x04>;
interrupt-names = "upg_bsc";
phandle = <0x05>;
};
spi0 {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-frequency = <0x19bfcc0>;
compatible = "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi";
reg = <0x00 0xd1217000 0x00 0x180>;
reg-names = "mspi";
interrupts = <0x00>;
interrupt-parent = <0x06>;
interrupt-names = "mspi_done";
phandle = <0x29>;
};
spi1 {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-frequency = <0x19bfcc0>;
compatible = "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi";
reg = <0x00 0xd1217400 0x00 0x180>;
reg-names = "mspi";
interrupts = <0x01>;
interrupt-parent = <0x06>;
interrupt-names = "mspi_done";
phandle = <0x2a>;
};
upg-spi-intc {
#interrupt-cells = <0x01>;
compatible = "brcm,bcm7271-l2-intc";
reg = <0x00 0xd1217800 0x00 0x10>;
interrupt-controller;
interrupt-parent = <0x01>;
interrupts = <0x00 0x24 0x04>;
interrupt-names = "upg_spi";
phandle = <0x06>;
};
upg-clk {
#clock-cells = <0x01>;
compatible = "fixed-clock";
clock-frequency = <0x19bfcc0>;
phandle = <0x07>;
};
upg_pwm0 {
#pwm-cells = <0x02>;
clocks = <0x07 0x00>;
compatible = "brcm,bcm7038-pwm", "brcm,brcmstb-pwm";
reg = <0x00 0xd1213040 0x00 0x28>;
};
watchdog0 {
clock-frequency = <0x19bfcc0>;
compatible = "brcm,bcm3390-wdt";
reg = <0x00 0xd1213700 0x00 0x40>;
interrupts = <0x00 0x28 0x04>;
interrupt-parent = <0x01>;
interrupt-names = "wd_timeout";
};
pinctrl-gpio {
compatible = "brcm,bcmrpc-pinctrl-gpio";
#gpio-cells = <0x02>;
#interrupt-cells = <0x02>;
gpio-controller;
interrupt-controller;
reg = <0x00 0xd1214000 0x00 0x100>;
gpio-names = "gpio";
gpio-pins-info = <0x00 0x100 0x03 0x07>;
interrupts = <0x00>;
interrupt-parent = <0x08>;
interrupt-names = "gio";
brcm,gpio-bank-widths = <0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20>;
rpc-channel = <0x09>;
phandle = <0x19>;
};
fpm {
compatible = "brcm,fpm";
reg = <0x00 0xdde00000 0x00 0x70000>;
track-tokens = <0x01>;
track-on-err = <0x00>;
lwm-watchdog-timeout = <0x493e0>;
phandle = <0x2b>;
};
dqmsmc {
compatible = "brcm,dqm";
reg = <0x00 0xd1000000 0x00 0x120790>;
dev-name = "smc";
q-data-base-offset = <0x105000>;
q-status-base-offset = <0x102800>;
q-mib-base-offset = <0x103000>;
q-count = <0x20>;
qsm-size = <0x8000>;
legacy-irq;
restricted-access;
phandle = <0x2c>;
dqmintc0 {
interrupt-parent = <0x01>;
interrupts = <0x00 0x16 0x04>;
interrupt-controller;
#interrupt-cells = <0x01>;
l1-irq-mask-offset = <0x120728>;
l1-irq-status-offset = <0x120724>;
l1-irq-type-offset = <0x12072c>;
l1-irq-dqm-mask = <0x02>;
lwm-irq-mask-offset = <0x101d3c>;
lwm-irq-status-offset = <0x101d34>;
ne-irq-mask-offset = <0x101d0c>;
ne-irq-status-offset = <0x101d04>;
ne-status-offset = <0x101d00>;
phandle = <0x0a>;
};
dqm0 {
qname = "RPC RG-->SMC (non-secure)";
id = <0x00>;
words = <0x04>;
depth = <0x10>;
lwm = <0x02>;
hwm = <0x01>;
interrupt-parent = <0x0a>;
interrupts = <0x00>;
phandle = <0x2d>;
};
dqm1 {
qname = "RPC SMC-->RG (non-secure)";
id = <0x01>;
words = <0x04>;
depth = <0x10>;
lwm = <0x02>;
hwm = <0x01>;
interrupt-parent = <0x0a>;
interrupts = <0x01>;
phandle = <0x2e>;
};
dqm10 {
qname = "RPC RG APPS-->SMC";
id = <0x0a>;
words = <0x04>;
depth = <0x08>;
lwm = <0x02>;
hwm = <0x01>;
interrupt-parent = <0x0a>;
interrupts = <0x0a>;
phandle = <0x2f>;
};
dqm11 {
qname = "RPC SMC-->RG APPS";
id = <0x0b>;
words = <0x04>;
depth = <0x08>;
lwm = <0x02>;
hwm = <0x01>;
interrupt-parent = <0x0a>;
interrupts = <0x0b>;
phandle = <0x30>;
};
};
gfap-dev {
compatible = "brcm,gfap";
gfap-top-base = <0x00 0xd2000000>;
phandle = <0x31>;
};
dqmgfap {
compatible = "brcm,dqm";
reg = <0x00 0xde100000 0x00 0x16800>;
dev-name = "gfap";
cfg-offset = <0x10000>;
q-ctl-base-offset = <0x12000 0x12400>;
q-tmr-base-offset = <0x10800 0x10900>;
q-data-base-offset = <0x14000 0x14400>;
q-status-base-offset = <0x10400 0x10480>;
q-mib-base-offset = <0x11000 0x11200>;
q-count = <0x40>;
offload;
live-irq;
interrupt-parent = <0x01>;
phandle = <0x32>;
dqmpc0 {
id = <0x00>;
phandle = <0x33>;
};
dqmpc1 {
id = <0x01>;
phandle = <0x34>;
};
dqmpc2 {
id = <0x02>;
phandle = <0x35>;
};
dqmpc3 {
id = <0x03>;
phandle = <0x36>;
};
dqmpc4 {
id = <0x04>;
phandle = <0x37>;
};
dqmpc5 {
id = <0x05>;
phandle = <0x38>;
};
dqmpc6 {
id = <0x06>;
phandle = <0x39>;
};
dqmpc7 {
id = <0x07>;
phandle = <0x3a>;
};
dqmpc8 {
id = <0x08>;
phandle = <0x3b>;
};
dqmpc9 {
id = <0x09>;
phandle = <0x3c>;
};
dqmpc10 {
id = <0x0a>;
phandle = <0x3d>;
};
dqmpc11 {
id = <0x0b>;
phandle = <0x3e>;
};
dqmpc12 {
id = <0x0c>;
phandle = <0x3f>;
};
dqmpc13 {
id = <0x0d>;
phandle = <0x40>;
};
dqmpc14 {
id = <0x0e>;
phandle = <0x41>;
};
dqmpc15 {
id = <0x0f>;
phandle = <0x42>;
};
dqmpc16 {
id = <0x10>;
interrupts = <0x00 0x90 0x01>;
live-irq-status-offset = <0x9040>;
live-irq-mask-offset = <0x9140 0x9240 0x9340>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x43>;
};
dqmpc17 {
id = <0x11>;
interrupts = <0x00 0x91 0x01>;
live-irq-status-offset = <0x9044>;
live-irq-mask-offset = <0x9144 0x9244 0x9344>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x44>;
};
dqmpc18 {
id = <0x12>;
interrupts = <0x00 0x92 0x01>;
live-irq-status-offset = <0x9048>;
live-irq-mask-offset = <0x9148 0x9248 0x9348>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x45>;
};
dqmpc19 {
id = <0x13>;
interrupts = <0x00 0x93 0x01>;
live-irq-status-offset = <0x904c>;
live-irq-mask-offset = <0x914c 0x924c 0x934c>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x46>;
};
dqmpc20 {
id = <0x14>;
interrupts = <0x00 0x94 0x01>;
live-irq-status-offset = <0x9050>;
live-irq-mask-offset = <0x9150 0x9250 0x9350>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x47>;
};
dqmpc21 {
id = <0x15>;
interrupts = <0x00 0x95 0x01>;
live-irq-status-offset = <0x9054>;
live-irq-mask-offset = <0x9154 0x9254 0x9354>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x48>;
};
dqmpc22 {
id = <0x16>;
interrupts = <0x00 0x96 0x01>;
live-irq-status-offset = <0x9058>;
live-irq-mask-offset = <0x9158 0x9258 0x9358>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x49>;
};
dqmpc23 {
id = <0x17>;
interrupts = <0x00 0x97 0x01>;
live-irq-status-offset = <0x905c>;
live-irq-mask-offset = <0x915c 0x925c 0x935c>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x4a>;
};
dqmpc24 {
id = <0x18>;
interrupts = <0x00 0x98 0x01>;
live-irq-status-offset = <0x9060>;
live-irq-mask-offset = <0x9160 0x9260 0x9360>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x4b>;
};
dqmpc25 {
id = <0x19>;
interrupts = <0x00 0x99 0x01>;
live-irq-status-offset = <0x9064>;
live-irq-mask-offset = <0x9164 0x9264 0x9364>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x4c>;
};
dqmpc26 {
id = <0x1a>;
interrupts = <0x00 0x9a 0x01>;
live-irq-status-offset = <0x9068>;
live-irq-mask-offset = <0x9168 0x9268 0x9368>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x4d>;
};
dqmpc27 {
id = <0x1b>;
interrupts = <0x00 0x9b 0x01>;
live-irq-status-offset = <0x906c>;
live-irq-mask-offset = <0x916c 0x926c 0x936c>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x4e>;
};
dqmpc28 {
id = <0x1c>;
interrupts = <0x00 0x9c 0x01>;
live-irq-status-offset = <0x9070>;
live-irq-mask-offset = <0x9170 0x9270 0x9370>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x4f>;
};
dqmpc29 {
id = <0x1d>;
interrupts = <0x00 0x9d 0x01>;
live-irq-status-offset = <0x9074>;
live-irq-mask-offset = <0x9174 0x9274 0x9374>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x50>;
};
dqmpc30 {
id = <0x1e>;
interrupts = <0x00 0x9e 0x01>;
live-irq-status-offset = <0x9078>;
live-irq-mask-offset = <0x9178 0x9278 0x9378>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x51>;
};
dqmpc31 {
id = <0x1f>;
interrupts = <0x00 0x9f 0x01>;
live-irq-status-offset = <0x907c>;
live-irq-mask-offset = <0x917c 0x927c 0x937c>;
live-irq-tmr-status-offset = <0x10248 0x10250 0x10258>;
phandle = <0x52>;
};
dqmpc32 {
id = <0x20>;
phandle = <0x53>;
};
dqmpc33 {
id = <0x21>;
phandle = <0x54>;
};
dqmpc34 {
id = <0x22>;
phandle = <0x55>;
};
dqmpc35 {
id = <0x23>;
phandle = <0x56>;
};
dqmpc36 {
id = <0x24>;
phandle = <0x57>;
};
dqmpc37 {
id = <0x25>;
phandle = <0x58>;
};
dqmpc38 {
id = <0x26>;
phandle = <0x59>;
};
dqmpc39 {
id = <0x27>;
phandle = <0x5a>;
};
dqmpc40 {
id = <0x28>;
interrupts = <0x00 0xa8 0x01>;
live-irq-status-offset = <0x90a0>;
live-irq-mask-offset = <0x91a0 0x92a0 0x93a0>;
live-irq-tmr-status-offset = <0x1024c 0x10254 0x1025c>;
phandle = <0x5b>;
};
dqmpc41 {
id = <0x29>;
interrupts = <0x00 0xa9 0x01>;
live-irq-status-offset = <0x90a4>;
live-irq-mask-offset = <0x91a4 0x92a4 0x93a4>;
live-irq-tmr-status-offset = <0x1024c 0x10254 0x1025c>;
phandle = <0x5c>;
};
dqmpc42 {
id = <0x2a>;
interrupts = <0x00 0xaa 0x01>;
live-irq-status-offset = <0x90a8>;
live-irq-mask-offset = <0x91a8 0x92a8 0x93a8>;
live-irq-tmr-status-offset = <0x1024c 0x10254 0x1025c>;
phandle = <0x5d>;
};
dqmpc43 {
id = <0x2b>;
interrupts = <0x00 0xab 0x01>;
live-irq-status-offset = <0x90ac>;
live-irq-mask-offset = <0x91ac 0x92ac 0x93ac>;
live-irq-tmr-status-offset = <0x1024c 0x10254 0x1025c>;
phandle = <0x5e>;
};
dqmpc44 {
id = <0x2c>;
interrupts = <0x00 0xac 0x01>;
live-irq-status-offset = <0x90b0>;
live-irq-mask-offset = <0x91b0 0x92b0 0x93b0>;
live-irq-tmr-status-offset = <0x1024c 0x10254 0x1025c>;
phandle = <0x5f>;
};
dqmpc45 {
id = <0x2d>;
interrupts = <0x00 0xad 0x01>;
live-irq-status-offset = <0x90b4>;
live-irq-mask-offset = <0x91b4 0x92b4 0x93b4>;
live-irq-tmr-status-offset = <0x1024c 0x10254 0x1025c>;
phandle = <0x60>;
};
dqmpc46 {
id = <0x2e>;
interrupts = <0x00 0xae 0x01>;
live-irq-status-offset = <0x90b8>;
live-irq-mask-offset = <0x91b8 0x92b8 0x93b8>;
live-irq-tmr-status-offset = <0x1024c 0x10254 0x1025c>;
phandle = <0x61>;
};
dqmpc47 {
id = <0x2f>;
interrupts = <0x00 0xaf 0x01>;
live-irq-status-offset = <0x90bc>;
live-irq-mask-offset = <0x91bc 0x92bc 0x93bc>;
live-irq-tmr-status-offset = <0x1024c 0x10254 0x1025c>;
phandle = <0x62>;
};
};
dqmep5 {
compatible = "brcm,dqm";
reg = <0x00 0xdad00000 0x00 0xf080>;
dev-name = "ep5";
cfg-offset = <0x8000>;
q-ctl-base-offset = <0xa000>;
q-tmr-base-offset = <0x8800>;
q-data-base-offset = <0xc000>;
q-status-base-offset = <0x8400>;
q-mib-base-offset = <0x9000>;
q-count = <0x20>;
offload;
ext-irq;
phandle = <0x63>;
dqmep5intc0 {
interrupt-parent = <0x01>;
interrupts = <0x00 0x6c 0x04>;
interrupt-controller;
#interrupt-cells = <0x01>;
l1-irq-dqm-mask = <0x36>;
l1-irq-status-offset = <0x1800>;
ne-irq-mask-offset = <0x18e0 0x1900 0x1920>;
ne-irq-status-offset = <0x1618 0x1620 0x1628>;
tmr-irq-mask-offset = <0x1940 0x1960 0x1980>;
tmr-irq-status-offset = <0x1648 0x1650 0x1658>;
lwm-irq-mask-offset = <0x19a0 0x19c0 0x19e0>;
lwm-irq-status-offset = <0x1678 0x1680 0x1688>;
hwm-irq-mask-offset = <0x1a00 0x1a20 0x1a40>;
hwm-irq-status-offset = <0x16a8 0x16b0 0x16b8>;
phandle = <0x0b>;
};
dqmep50 {
qname = "Ep5ToHost_CtrlSlot";
id = <0x00>;
phandle = <0x64>;
};
dqmep51 {
qname = "HostToEp5_CtrlSlot";
id = <0x01>;
phandle = <0x65>;
};
dqmep52 {
qname = "HostToEp5_REQ";
id = <0x02>;
phandle = <0x66>;
};
dqmep53 {
qname = "HostToEp5_RSP";
id = <0x03>;
phandle = <0x67>;
};
dqmep54 {
qname = "HostToEp5_Event";
id = <0x04>;
phandle = <0x68>;
};
dqmep55 {
qname = "Ep5ToHost_REQ";
id = <0x05>;
words = <0x01>;
interrupt-parent = <0x0b>;
interrupts = <0x05 0x04>;
phandle = <0x69>;
};
dqmep56 {
qname = "Ep5ToHost_RSP";
id = <0x06>;
words = <0x01>;
interrupt-parent = <0x0b>;
interrupts = <0x06 0x04>;
phandle = <0x6a>;
};
dqmep57 {
qname = "Ep5ToHost_Event";
id = <0x07>;
words = <0x01>;
interrupt-parent = <0x0b>;
interrupts = <0x07 0x04>;
phandle = <0x6b>;
};
};
dqmcpuc {
compatible = "brcm,dqm";
reg = <0x00 0xd1240000 0x00 0xa180>;
offload;
dev-name = "cpucomm";
cfg-offset = <0x1c00>;
q-ctl-base-offset = <0x8000>;
q-tmr-base-offset = <0x2000>;
q-data-base-offset = <0x9000>;
q-status-base-offset = <0x7400>;
q-mib-base-offset = <0xa000>;
q-count = <0x20>;
qsm-size = <0xc000>;
legacy-irq;
phandle = <0x6c>;
cdqmintc0 {
interrupts = <0x00 0xc4 0x04>;
interrupt-controller;
#interrupt-cells = <0x01>;
interrupt-parent = <0x01>;
l1-irq-mask-offset = <0x50>;
l1-irq-status-offset = <0x54>;
l1-irq-dqm-mask = <0x400000>;
lwm-irq-mask-offset = <0x1cb0>;
lwm-irq-status-offset = <0x1ca0>;
ne-irq-mask-offset = <0x1c20>;
ne-irq-status-offset = <0x1c10>;
ne-status-offset = <0x1c14>;
hwm-irq-mask-offset = <0x1c80>;
hwm-irq-status-offset = <0x1c70>;
tmr-irq-mask-offset = <0x1c50>;
tmr-irq-status-offset = <0x1c40>;
phandle = <0x0c>;
};
dqm2 {
qname = "RPC RG-->CM";
id = <0x02>;
words = <0x04>;
depth = <0x08>;
lwm = <0x02>;
hwm = <0x01>;
interrupt-parent = <0x0c>;
interrupts = <0x02>;
phandle = <0x6d>;
};
dqm3 {
qname = "RPC RG<--CM";
id = <0x03>;
words = <0x04>;
depth = <0x08>;
lwm = <0x02>;
hwm = <0x01>;
interrupt-parent = <0x0c>;
interrupts = <0x03>;
phandle = <0x6e>;
};
dqm14 {
qname = "Private Network RG-->CM";
id = <0x0e>;
words = <0x02>;
depth = <0x10>;
lwm = <0x04>;
hwm = <0x01>;
interrupt-parent = <0x0c>;
interrupts = <0x0e>;
phandle = <0x6f>;
};
dqm15 {
qname = "Private Network RG<--CM";
id = <0x0f>;
words = <0x02>;
depth = <0x40>;
lwm = <0x04>;
hwm = <0x01>;
interrupt-parent = <0x0c>;
interrupts = <0x0f>;
phandle = <0x70>;
};
dqm20 {
qname = "RPC SVM-->CM";
id = <0x14>;
words = <0x04>;
depth = <0x08>;
lwm = <0x02>;
hwm = <0x01>;
interrupt-parent = <0x0c>;
interrupts = <0x14>;
phandle = <0x71>;
};
dqm21 {
qname = "RPC SVM<--CM";
id = <0x15>;
words = <0x04>;
depth = <0x08>;
lwm = <0x02>;
hwm = <0x01>;
interrupt-parent = <0x0c>;
interrupts = <0x15>;
phandle = <0x72>;
};
};
netport {
compatible = "brcm,netport";
reg = <0x00 0xe3800000 0x00 0x5c00>;
dev-name = "netport";
phandle = <0x73>;
};
merlin {
status = "disabled";
compatible = "brcm,merlin16-shasta";
reg = <0x00 0xe3805c00 0x00 0x60>;
dev-name = "merlin";
merlin-refsel = "CML refclk";
merlin-pllclk = "54 MHz";
merlin-plldiv = "190.97222";
phandle = <0x74>;
};
netport-mdio {
compatible = "brcm,unimac-mdio";
reg = <0x00 0xe3805400 0x00 0x08>;
dev-name = "Netport MII bus";
reg-names = "netport_mdio";
clock-frequency = <0xad6534>;
phandle = <0x75>;
};
miimdiomux {
compatible = "brcm,miimdiomux339x";
reg = <0x00 0xe38041b0 0x00 0x04>;
mdio_c_en = "disable";
mdio_b_en = "disable";
mdio_a_en = "disable";
alt_rgmii = "a";
phandle = <0x76>;
};
unimac0 {
status = "disabled";
compatible = "brcm,unimac";
reg = <0x00 0xe3802000 0x00 0x1000>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x79 0x04 0x00 0x7a 0x04>;
unimac_core_offset = <0x400>;
unimac_iface_offset = <0x00>;
unimac_mib_offset = <0x800>;
dev-name = "unimac0";
phandle = <0x77>;
};
unimac1 {
status = "disabled";
compatible = "brcm,unimac";
reg = <0x00 0xe3803000 0x00 0x1000>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x79 0x04 0x00 0x7a 0x04>;
unimac_core_offset = <0x400>;
unimac_iface_offset = <0x00>;
unimac_mib_offset = <0x800>;
dev-name = "unimac1";
phandle = <0x78>;
};
xlmac0 {
status = "disabled";
compatible = "brcm,xlmac";
mac-access = "mac-dir0-access";
mib-access = "mib-dir0-access";
dev-name = "xlmac0";
phandle = <0x79>;
};
xlmac1 {
status = "disabled";
compatible = "brcm,xlmac";
mac-access = "mac-dir0-access";
mib-access = "mib-dir0-access";
dev-name = "xlmac1";
phandle = <0x7a>;
};
xlmac2 {
status = "disabled";
compatible = "brcm,xlmac";
mac-access = "mac-dir0-access";
mib-access = "mib-dir0-access";
dev-name = "xlmac2";
phandle = <0x7b>;
};
xlmac3 {
status = "disabled";
compatible = "brcm,xlmac";
mac-access = "mac-dir0-access";
mib-access = "mib-dir0-access";
dev-name = "xlmac3";
phandle = <0x7c>;
};
dgphy0 {
status = "disabled";
compatible = "brcm,dgphy";
dev-name = "dgphy0";
phandle = <0x7d>;
};
dgphy1 {
status = "disabled";
compatible = "brcm,dgphy";
dev-name = "dgphy1";
phandle = <0x7e>;
};
rgmii0 {
status = "disabled";
compatible = "brcm,rgmii";
dev-name = "rgmii0";
phandle = <0x7f>;
};
rgmii1 {
status = "disabled";
compatible = "brcm,rgmii";
dev-name = "rgmii1";
phandle = <0x80>;
};
lane0 {
status = "disabled";
compatible = "brcm,merlin16-shasta-lane";
serdes-access = "serdes-ind0-access";
dev-name = "serdes0";
phandle = <0x81>;
};
lane1 {
status = "disabled";
compatible = "brcm,merlin16-shasta-lane";
serdes-access = "serdes-ind1-access";
dev-name = "serdes1";
phandle = <0x82>;
};
lane2 {
status = "disabled";
compatible = "brcm,merlin16-shasta-lane";
serdes-access = "serdes-ind0-access";
dev-name = "serdes2";
phandle = <0x83>;
};
lane3 {
status = "disabled";
compatible = "brcm,merlin16-shasta-lane";
serdes-access = "serdes-ind1-access";
dev-name = "serdes3";
phandle = <0x84>;
};
pcie0-l2-intc {
status = "disabled";
reg = <0x00 0xc0009400 0x00 0x10>;
compatible = "brcm,bcm7271-l2-intc";
interrupt-controller;
#interrupt-cells = <0x01>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x76 0x04>;
interrupt-names = "pcie_0";
phandle = <0x0f>;
};
pcie1-l2-intc {
status = "disabled";
reg = <0x00 0xc4009400 0x00 0x10>;
compatible = "brcm,bcm7271-l2-intc";
interrupt-controller;
#interrupt-cells = <0x01>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x77 0x04>;
interrupt-names = "pcie_1";
phandle = <0x11>;
};
pcie2-l2-intc {
status = "disabled";
reg = <0x00 0xc8009400 0x00 0x10>;
compatible = "brcm,bcm7271-l2-intc";
interrupt-controller;
#interrupt-cells = <0x01>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x78 0x04>;
interrupt-names = "pcie_2";
phandle = <0x13>;
};
pcie3-l2-intc {
status = "disabled";
reg = <0x00 0xcc009400 0x00 0x10>;
compatible = "brcm,bcm7271-l2-intc";
interrupt-controller;
#interrupt-cells = <0x01>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x79 0x04>;
interrupt-names = "pcie_3";
phandle = <0x15>;
};
iproc-pdc {
compatible = "brcm,iproc-pdc-mbox";
reg = <0x00 0xddc00000 0x00 0x448>;
interrupts = <0x00 0x3d 0x04>;
#mbox-cells = <0x01>;
brcm,rx-status-len = <0x04>;
brcm,use-bcm-hdr;
phandle = <0x0d>;
};
crypto {
compatible = "brcm,spum-crypto";
reg = <0x00 0xddc01000 0x00 0x1010>;
mboxes = <0x0d 0x00>;
};
spu_pdc {
status = "disabled";
compatible = "brcm,spu-pdc";
reg = <0x00 0xddc00000 0x00 0x448>;
interrupts = <0x00 0x3d 0x04>;
brcm,num_chan = <0x01>;
phandle = <0x85>;
};
spu_crypto {
status = "disabled";
compatible = "brcm,spu-crypto";
reg = <0x00 0xddc01000 0x00 0x1010>;
brcm,num_spu = <0x01>;
brcm,spu_type = <0x01>;
phandle = <0x86>;
};
spu_flexrm {
status = "disabled";
compatible = "brcm,spu-flexrm";
reg = <0x00 0xd1800000 0x00 0x2810b0>;
interrupts = <0x00 0xc9 0x04 0x00 0xca 0x04 0x00 0xcb 0x04 0x00 0xcc 0x04>;
brcm,num_chan = <0x04>;
brcm,num_ae = <0x02>;
phandle = <0x87>;
};
spu_crypto2 {
status = "disabled";
compatible = "brcm,spu-crypto";
reg = <0x00 0xd1ac0000 0x00 0x8f>;
brcm,num_spu = <0x01>;
brcm,spu_type = <0x02>;
phandle = <0x88>;
};
usbphy-0 {
reg = <0x00 0xdf80f200 0x00 0x200 0x00 0xdf80c100 0x00 0x544 0x00 0xdf80fc00 0x00 0xff>;
reg-names = "ctrl", "xhci_gbl", "usb_tca";
#address-cells = <0x02>;
#size-cells = <0x02>;
status = "disabled";
compatible = "brcm,bcm33940xc0-usb-phy", "brcm,brcmstb-usb-phy", "brcm,usb-phy";
#phy-cells = <0x01>;
ranges;
has_xhci_only;
brcm,has-xhci;
brcm,tx_preempamp_tune0 = <0x03>;
phandle = <0x0e>;
};
xhci-v2-0 {
compatible = "brcm,xhci-brcm-v2", "generic-xhci";
status = "disabled";
reg = <0x00 0xdf800000 0x00 0x2004>;
interrupts = <0x00 0x7b 0x04>;
interrupt-names = "usb0_xhci_0";
phys = <0x0e 0x01>;
phy-names = "usbphy";
phandle = <0x89>;
};
system_bus {
compatible = "simple-bus";
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
sdhci-0 {
status = "disabled";
compatible = "brcm,bcm33940-sdhci", "brcm,bcm3392-sdhci", "brcm,bcm7216-sdhci", "brcm,bcm7445-sdhci", "brcm,sdhci-brcmstb";
reg = <0x00 0xd1200000 0x00 0x260 0x00 0xd1200400 0x00 0x200>;
reg-names = "host", "cfg";
interrupt-parent = <0x01>;
interrupts = <0x00 0x30 0x04>;
interrupt-names = "sdio0_0";
sd-uhs-ddr50;
sd-uhs-sdr50;
sd-uhs-sdr104;
sdhci,auto-cmd12;
phandle = <0x8a>;
};
};
pcie@c0000000 {
status = "disabled";
reg = <0x00 0xc0000000 0x00 0x9508>;
#address-cells = <0x03>;
#size-cells = <0x02>;
ranges = <0x3000000 0x00 0x00 0x03 0x00 0x00 0x40000000>;
dma-ranges = <0x3000000 0x06 0x00 0x06 0x00 0x01 0x00 0x3000000 0x05 0x00 0x05 0x00 0x01 0x00 0x3000000 0x04 0x00 0x04 0x00 0x01 0x00 0x3000000 0x12 0x80000000 0x02 0x80000000 0x00 0x40000000 0x3000000 0x12 0x00 0x02 0x00 0x00 0x80000000 0x3000000 0x11 0x00 0x01 0x00 0x00 0x80000000 0x3000000 0x10 0xda000000 0x00 0xda000000 0x00 0x1000000 0x3000000 0x10 0x80000000 0x00 0x80000000 0x00 0x40000000 0x3000000 0x10 0x00 0x00 0x00 0x00 0x80000000>;
tot-num-pcie = <0x01>;
interrupt-parent = <0x0f>;
interrupts = <0x05 0x09>;
interrupt-names = "pcie0", "pcie0_msi";
msi-parent = <0x10>;
msi-controller;
#interrupt-cells = <0x01>;
interrupt-map-mask = <0xf800 0x00 0x00 0x07>;
interrupt-map = <0x00 0x00 0x00 0x01 0x0f 0x01 0x00 0x00 0x00 0x02 0x0f 0x02 0x00 0x00 0x00 0x03 0x0f 0x03 0x00 0x00 0x00 0x04 0x0f 0x04>;
max-link-speed = <0x03>;
device_type = "pci";
bus-range = <0x00 0xff>;
linux,pci-domain = <0x00>;
phandle = <0x10>;
pci@0,0 {
reg = <0x00 0x00 0x00 0x00 0x00>;
compatible = "pciclass,0604";
device_type = "pci";
#address-cells = <0x03>;
#size-cells = <0x02>;
};
};
pcie@c4000000 {
status = "disabled";
reg = <0x00 0xc4000000 0x00 0x9508>;
#address-cells = <0x03>;
#size-cells = <0x02>;
ranges = <0x3000000 0x00 0x00 0x04 0x00 0x00 0x40000000>;
dma-ranges = <0x3000000 0x06 0x00 0x06 0x00 0x01 0x00 0x3000000 0x05 0x00 0x05 0x00 0x01 0x00 0x3000000 0x03 0x00 0x03 0x00 0x01 0x00 0x3000000 0x12 0x80000000 0x02 0x80000000 0x00 0x40000000 0x3000000 0x12 0x00 0x02 0x00 0x00 0x80000000 0x3000000 0x11 0x00 0x01 0x00 0x00 0x80000000 0x3000000 0x10 0xda000000 0x00 0xda000000 0x00 0x1000000 0x3000000 0x10 0x80000000 0x00 0x80000000 0x00 0x40000000 0x3000000 0x10 0x00 0x00 0x00 0x00 0x80000000>;
tot-num-pcie = <0x01>;
interrupt-parent = <0x11>;
interrupts = <0x05 0x09>;
interrupt-names = "pcie1", "pcie1_msi";
msi-parent = <0x12>;
msi-controller;
#interrupt-cells = <0x01>;
interrupt-map-mask = <0xf800 0x00 0x00 0x07>;
interrupt-map = <0x00 0x00 0x00 0x01 0x11 0x01 0x00 0x00 0x00 0x02 0x11 0x02 0x00 0x00 0x00 0x03 0x11 0x03 0x00 0x00 0x00 0x04 0x11 0x04>;
max-link-speed = <0x03>;
device_type = "pci";
bus-range = <0x00 0xff>;
linux,pci-domain = <0x01>;
phandle = <0x12>;
pci@0,0 {
reg = <0x00 0x00 0x00 0x00 0x00>;
compatible = "pciclass,0604";
device_type = "pci";
#address-cells = <0x03>;
#size-cells = <0x02>;
};
};
pcie@c8000000 {
status = "disabled";
reg = <0x00 0xc8000000 0x00 0x9508>;
#address-cells = <0x03>;
#size-cells = <0x02>;
ranges = <0x3000000 0x00 0x00 0x05 0x00 0x00 0x40000000>;
dma-ranges = <0x3000000 0x06 0x00 0x06 0x00 0x01 0x00 0x3000000 0x04 0x00 0x04 0x00 0x01 0x00 0x3000000 0x03 0x00 0x03 0x00 0x01 0x00 0x3000000 0x12 0x80000000 0x02 0x80000000 0x00 0x40000000 0x3000000 0x12 0x00 0x02 0x00 0x00 0x80000000 0x3000000 0x11 0x00 0x01 0x00 0x00 0x80000000 0x3000000 0x10 0xda000000 0x00 0xda000000 0x00 0x1000000 0x3000000 0x10 0x80000000 0x00 0x80000000 0x00 0x40000000 0x3000000 0x10 0x00 0x00 0x00 0x00 0x80000000>;
tot-num-pcie = <0x01>;
interrupt-parent = <0x13>;
interrupts = <0x05 0x09>;
interrupt-names = "pcie2", "pcie2_msi";
msi-parent = <0x14>;
msi-controller;
#interrupt-cells = <0x01>;
interrupt-map-mask = <0xf800 0x00 0x00 0x07>;
interrupt-map = <0x00 0x00 0x00 0x01 0x13 0x01 0x00 0x00 0x00 0x02 0x13 0x02 0x00 0x00 0x00 0x03 0x13 0x03 0x00 0x00 0x00 0x04 0x13 0x04>;
max-link-speed = <0x03>;
device_type = "pci";
bus-range = <0x00 0xff>;
linux,pci-domain = <0x02>;
phandle = <0x14>;
pci@0,0 {
reg = <0x00 0x00 0x00 0x00 0x00>;
compatible = "pciclass,0604";
device_type = "pci";
#address-cells = <0x03>;
#size-cells = <0x02>;
};
};
pcie@cc000000 {
status = "disabled";
reg = <0x00 0xcc000000 0x00 0x9508>;
#address-cells = <0x03>;
#size-cells = <0x02>;
ranges = <0x3000000 0x00 0x00 0x06 0x00 0x00 0x40000000>;
dma-ranges = <0x3000000 0x05 0x00 0x05 0x00 0x01 0x00 0x3000000 0x04 0x00 0x04 0x00 0x01 0x00 0x3000000 0x03 0x00 0x03 0x00 0x01 0x00 0x3000000 0x12 0x80000000 0x02 0x80000000 0x00 0x40000000 0x3000000 0x12 0x00 0x02 0x00 0x00 0x80000000 0x3000000 0x11 0x00 0x01 0x00 0x00 0x80000000 0x3000000 0x10 0xda000000 0x00 0xda000000 0x00 0x1000000 0x3000000 0x10 0x80000000 0x00 0x80000000 0x00 0x40000000 0x3000000 0x10 0x00 0x00 0x00 0x00 0x80000000>;
tot-num-pcie = <0x01>;
interrupt-parent = <0x15>;
interrupts = <0x05 0x09>;
interrupt-names = "pcie3", "pcie3_msi";
msi-parent = <0x16>;
msi-controller;
#interrupt-cells = <0x01>;
interrupt-map-mask = <0xf800 0x00 0x00 0x07>;
interrupt-map = <0x00 0x00 0x00 0x01 0x15 0x01 0x00 0x00 0x00 0x02 0x15 0x02 0x00 0x00 0x00 0x03 0x15 0x03 0x00 0x00 0x00 0x04 0x15 0x04>;
max-link-speed = <0x03>;
device_type = "pci";
bus-range = <0x00 0xff>;
linux,pci-domain = <0x03>;
phandle = <0x16>;
pci@0,0 {
reg = <0x00 0x00 0x00 0x00 0x00>;
compatible = "pciclass,0604";
device_type = "pci";
#address-cells = <0x03>;
#size-cells = <0x02>;
};
};
q-channel0 {
dev-name = "exc-eth0";
dqm = "gfap";
tx-q = <0xff>;
rx-q = <0xff>;
type = "fap-exception";
q-msg-fmt = "gfap3-fpm";
phandle = <0x8b>;
};
q-channel1 {
dev-name = "exc-eth1";
dqm = "gfap";
tx-q = <0xff>;
rx-q = <0xff>;
type = "fap-exception";
q-msg-fmt = "gfap3-fpm";
phandle = <0x8c>;
};
q-channel2 {
dev-name = "exc-eth2";
dqm = "gfap";
tx-q = <0xff>;
rx-q = <0xff>;
type = "fap-exception";
q-msg-fmt = "gfap3-fpm";
phandle = <0x8d>;
};
q-channel3 {
dev-name = "exc-eth3";
dqm = "gfap";
tx-q = <0xff>;
rx-q = <0xff>;
type = "fap-exception";
q-msg-fmt = "gfap3-fpm";
phandle = <0x8e>;
};
q-channel4 {
dev-name = "exc-eth4";
dqm = "gfap";
tx-q = <0xff>;
rx-q = <0xff>;
type = "fap-exception";
q-msg-fmt = "gfap3-fpm";
phandle = <0x8f>;
};
q-channel5 {
dev-name = "exc-eth5";
dqm = "gfap";
tx-q = <0xff>;
rx-q = <0xff>;
type = "fap-exception";
q-msg-fmt = "gfap3-fpm";
phandle = <0x90>;
};
q-channel6 {
dev-name = "exp-wl0";
dqm = "gfap";
tx-q = <0xff>;
rx-q = <0xff>;
type = "fap-exception";
q-msg-fmt = "gfap3-fpm";
phandle = <0x91>;
};
q-channel7 {
dev-name = "exp-wl1";
dqm = "gfap";
tx-q = <0xff>;
rx-q = <0xff>;
type = "fap-exception";
q-msg-fmt = "gfap3-fpm";
phandle = <0x92>;
};
q-channel8 {
dev-name = "exp-wl2";
dqm = "gfap";
tx-q = <0xff>;
rx-q = <0xff>;
type = "fap-exception";
q-msg-fmt = "gfap3-fpm";
phandle = <0x93>;
};
q-channel9 {
dev-name = "exc-cm0";
dqm = "gfap";
tx-q = <0xff>;
rx-q = <0xff>;
type = "fap-host";
q-msg-fmt = "gfap3-fpm";
phandle = <0x94>;
};
q-channelpriv0 {
dev-name = "cm-rg-priv0";
dqm = "cpucomm";
tx-q = <0x0e>;
rx-q = <0x0f>;
type = "point-to-point";
q-msg-fmt = "gfap-fpm";
phandle = <0x17>;
};
priv0 {
compatible = "brcm,dqnet";
channel = <0x17>;
dev-name = "priv0";
demux = "none";
link-type = "rpc";
rpc-channel = <0x18>;
phandle = <0x95>;
};
rpc {
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x00>;
rpc-version = <0x204>;
rpcrgsmc@0 {
reg = <0x00>;
compatible = "brcm,itc-rpc";
dev-name = "rg-smc";
fifo-dev = "smc";
tx-fifo = <0x00>;
rx-fifo = <0x01>;
phandle = <0x09>;
};
rpcrgappsmc@a {
reg = <0x0a>;
compatible = "brcm,itc-rpc";
dev-name = "rg-app-smc";
fifo-dev = "smc";
tx-fifo = <0x0a>;
rx-fifo = <0x0b>;
phandle = <0x96>;
};
rpcrgcm@2 {
reg = <0x02>;
compatible = "brcm,itc-rpc";
dev-name = "rg-cm";
fifo-dev = "cpucomm";
tx-fifo = <0x02>;
rx-fifo = <0x03>;
phandle = <0x18>;
};
};
rpcsmcramlog {
compatible = "brcm,smcramlog-rpc";
rpc-channel = <0x09>;
phandle = <0x97>;
};
bstm {
status = "disabled";
compatible = "brcm,bstm-v1.0.0.1";
reg = <0x00 0xdf000000 0x00 0xb030>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x3e 0x04>;
interrupt-names = "bstm";
phandle = <0x98>;
};
gpu {
status = "disabled";
compatible = "brcm,bcm33940-gpu", "brcm,gpu-v7.1.6.4";
reg = <0x00 0xdfa00000 0x00 0x30f00>;
reg-names = "v3d";
interrupt-parent = <0x01>;
interrupts = <0x00 0xc0 0x04 0x00 0xc1 0x04>;
interrupt-names = "v3d", "v3d_hub";
};
gpu-mmu {
status = "disabled";
compatible = "brcm,bcm33940-v3d", "brcm,v3d-v7.1.6.4";
};
aliases {
pcie0 = "/pcie0";
pcie1 = "/pcie1";
pcie2 = "/pcie2";
serial0 = "/dbg-uarta";
watchdog1 = "/watchdog0";
};
tch_tacho1 {
compatible = "tch,tacho1-gpio";
dev-name = "tacho1-gpio";
tacho1-gpio = <0x19 0x13 0x00>;
interrupt-parent = <0x19>;
interrupts = <0x13 0x03>;
};
__symbols__ {
chosen = "/chosen";
reserved_memory = "/reserved-memory";
NWMBOX = "/reserved-memory/NWMBOX";
l2_cache = "/cpus/cache";
brcm_bogus_clk = "/brcm_bogus_clk";
brcm_scmi_mailbox = "/brcm-scmi-mailbox0";
brcm_pwr_rpc = "/power";
brcm_ba_rpc = "/ba-rpc";
brcm_scmi = "/brcm-scmi0";
scmi_dvfs = "/brcm-scmi0/protocol@13";
scmi_clock = "/brcm-scmi0/protocol@14";
scmi_sensor = "/brcm-scmi0/protocol@15";
scmi_brcm = "/brcm-scmi0/protocol@80";
gic = "/gic-intc";
dbg_uarta = "/dbg-uarta";
uarta = "/uarta";
uartd = "/uartd";
upg_intc = "/upg-intc";
i2c_a = "/i2c-a";
i2c_d = "/i2c-d";
upg_bsc_intc = "/upg-bsc-intc";
spi0 = "/spi0";
spi1 = "/spi1";
upg_spi_intc = "/upg-spi-intc";
upg_clk = "/upg-clk";
pinctrl_gpio = "/pinctrl-gpio";
fpm = "/fpm";
dqmsmc = "/dqmsmc";
dqmintc0 = "/dqmsmc/dqmintc0";
dqm0 = "/dqmsmc/dqm0";
dqm1 = "/dqmsmc/dqm1";
dqm10 = "/dqmsmc/dqm10";
dqm11 = "/dqmsmc/dqm11";
gfap_dev = "/gfap-dev";
dqmgfap = "/dqmgfap";
dqmpc0 = "/dqmgfap/dqmpc0";
dqmpc1 = "/dqmgfap/dqmpc1";
dqmpc2 = "/dqmgfap/dqmpc2";
dqmpc3 = "/dqmgfap/dqmpc3";
dqmpc4 = "/dqmgfap/dqmpc4";
dqmpc5 = "/dqmgfap/dqmpc5";
dqmpc6 = "/dqmgfap/dqmpc6";
dqmpc7 = "/dqmgfap/dqmpc7";
dqmpc8 = "/dqmgfap/dqmpc8";
dqmpc9 = "/dqmgfap/dqmpc9";
dqmpc10 = "/dqmgfap/dqmpc10";
dqmpc11 = "/dqmgfap/dqmpc11";
dqmpc12 = "/dqmgfap/dqmpc12";
dqmpc13 = "/dqmgfap/dqmpc13";
dqmpc14 = "/dqmgfap/dqmpc14";
dqmpc15 = "/dqmgfap/dqmpc15";
dqmpc16 = "/dqmgfap/dqmpc16";
dqmpc17 = "/dqmgfap/dqmpc17";
dqmpc18 = "/dqmgfap/dqmpc18";
dqmpc19 = "/dqmgfap/dqmpc19";
dqmpc20 = "/dqmgfap/dqmpc20";
dqmpc21 = "/dqmgfap/dqmpc21";
dqmpc22 = "/dqmgfap/dqmpc22";
dqmpc23 = "/dqmgfap/dqmpc23";
dqmpc24 = "/dqmgfap/dqmpc24";
dqmpc25 = "/dqmgfap/dqmpc25";
dqmpc26 = "/dqmgfap/dqmpc26";
dqmpc27 = "/dqmgfap/dqmpc27";
dqmpc28 = "/dqmgfap/dqmpc28";
dqmpc29 = "/dqmgfap/dqmpc29";
dqmpc30 = "/dqmgfap/dqmpc30";
dqmpc31 = "/dqmgfap/dqmpc31";
dqmpc32 = "/dqmgfap/dqmpc32";
dqmpc33 = "/dqmgfap/dqmpc33";
dqmpc34 = "/dqmgfap/dqmpc34";
dqmpc35 = "/dqmgfap/dqmpc35";
dqmpc36 = "/dqmgfap/dqmpc36";
dqmpc37 = "/dqmgfap/dqmpc37";
dqmpc38 = "/dqmgfap/dqmpc38";
dqmpc39 = "/dqmgfap/dqmpc39";
dqmpc40 = "/dqmgfap/dqmpc40";
dqmpc41 = "/dqmgfap/dqmpc41";
dqmpc42 = "/dqmgfap/dqmpc42";
dqmpc43 = "/dqmgfap/dqmpc43";
dqmpc44 = "/dqmgfap/dqmpc44";
dqmpc45 = "/dqmgfap/dqmpc45";
dqmpc46 = "/dqmgfap/dqmpc46";
dqmpc47 = "/dqmgfap/dqmpc47";
dqmep5 = "/dqmep5";
dqmep5intc0 = "/dqmep5/dqmep5intc0";
dqmep50 = "/dqmep5/dqmep50";
dqmep51 = "/dqmep5/dqmep51";
dqmep52 = "/dqmep5/dqmep52";
dqmep53 = "/dqmep5/dqmep53";
dqmep54 = "/dqmep5/dqmep54";
dqmep55 = "/dqmep5/dqmep55";
dqmep56 = "/dqmep5/dqmep56";
dqmep57 = "/dqmep5/dqmep57";
dqmcpuc = "/dqmcpuc";
cdqmintc0 = "/dqmcpuc/cdqmintc0";
dqm2 = "/dqmcpuc/dqm2";
dqm3 = "/dqmcpuc/dqm3";
dqm14 = "/dqmcpuc/dqm14";
dqm15 = "/dqmcpuc/dqm15";
dqm20 = "/dqmcpuc/dqm20";
dqm21 = "/dqmcpuc/dqm21";
netport = "/netport";
merlin = "/merlin";
netport_mdio = "/netport-mdio";
miimdiomux = "/miimdiomux";
unimac0 = "/unimac0";
unimac1 = "/unimac1";
xlmac0 = "/xlmac0";
xlmac1 = "/xlmac1";
xlmac2 = "/xlmac2";
xlmac3 = "/xlmac3";
dgphy0 = "/dgphy0";
dgphy1 = "/dgphy1";
rgmii0 = "/rgmii0";
rgmii1 = "/rgmii1";
xgmii0 = "/lane0";
xgmii1 = "/lane1";
xgmii2 = "/lane2";
xgmii3 = "/lane3";
pcie0_l2_intc = "/pcie0-l2-intc";
pcie1_l2_intc = "/pcie1-l2-intc";
pcie2_l2_intc = "/pcie2-l2-intc";
pcie3_l2_intc = "/pcie3-l2-intc";
pdc = "/iproc-pdc";
spu_pdc = "/spu_pdc";
spu_crypto = "/spu_crypto";
spu_flexrm = "/spu_flexrm";
spu_crypto2 = "/spu_crypto2";
usbphy_0 = "/usbphy-0";
xhci_0_0 = "/xhci-v2-0";
sdhci_0 = "/system_bus/sdhci-0";
pcie0 = "/pcie@c0000000";
pcie1 = "/pcie@c4000000";
pcie2 = "/pcie@c8000000";
pcie3 = "/pcie@cc000000";
qchan0 = "/q-channel0";
qchan1 = "/q-channel1";
qchan2 = "/q-channel2";
qchan3 = "/q-channel3";
qchan4 = "/q-channel4";
qchan5 = "/q-channel5";
qchan6 = "/q-channel6";
qchan7 = "/q-channel7";
qchan8 = "/q-channel8";
qchan9 = "/q-channel9";
qchanpriv0 = "/q-channelpriv0";
priv0 = "/priv0";
rpcrgsmc = "/rpc/rpcrgsmc@0";
rpcrgappsmc = "/rpc/rpcrgappsmc@a";
rpcrgcm = "/rpc/rpcrgcm@2";
rpcsmcramlog = "/rpcsmcramlog";
bstm = "/bstm";
};
};
And the BCM33940/BCM33941 specific trees:
BCM33940/BCM33941 Device Tree
/dts-v1/;
/ {
compatible = "brcm,bcm33940", "brcm,bcm33941";
platform-match {
layer = <0x20>;
match = "a | b | c | d | e | f | g | h | i | j | k | l | m | n";
a {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xfb350000>;
};
b {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf9390000>;
};
c {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf0a90000>;
};
d {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xff4c0000>;
};
e {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf0c40000>;
};
f {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf0c70000>;
};
g {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xfecb0000>;
};
h {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf0600000>;
};
i {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xfa890000>;
};
j {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf22c0000>;
};
k {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xff130000>;
};
l {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf8440000>;
};
m {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf4f30000>;
};
n {
type = "rpc";
request = <0x20f1000 0x00 0x00 0x00>;
mask = <0xffffff00 0x00 0x00 0xffffff00>;
val = <0x30f1000 0x00 0x00 0xf7300000>;
};
};
fragment@0 {
target = <0xffffffff>;
__overlay__ {
compatible = "brcm,bcm33940-pcie";
};
};
fragment@1 {
target = <0xffffffff>;
__overlay__ {
compatible = "brcm,bcm33940-pcie";
};
};
fragment@2 {
target = <0xffffffff>;
__overlay__ {
compatible = "brcm,bcm33940-pcie";
};
};
fragment@3 {
target = <0xffffffff>;
__overlay__ {
compatible = "brcm,bcm33940-pcie";
};
};
__fixups__ {
pcie0 = "/fragment@0:target:0";
pcie1 = "/fragment@1:target:0";
pcie2 = "/fragment@2:target:0";
pcie3 = "/fragment@3:target:0";
};
};
So far, these chips are found in the CGM601TCOM and SG417DBCT from Comcast. The firmware updates are fully encrypted as well.