PDP-1(D) in Verilog

Basic usage

Adjust the readmemh pdp1_memory.v to load a hex dump of some program (default is "test.hex")
The simulation will stop if the more than 1000000000 cycles have passed or if CPU is halted over the OPR instruction or gets an unknown instruction.
Default output is pdp1.vcd

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
LICENSE		LICENSE
README.md		README.md
pdp1_alu.v		pdp1_alu.v
pdp1_cpu.v		pdp1_cpu.v
pdp1_defs.v		pdp1_defs.v
pdp1_iot.v		pdp1_iot.v
pdp1_memory.v		pdp1_memory.v
pdp1_opr_decoder.v		pdp1_opr_decoder.v
pdp1_sbs.v		pdp1_sbs.v
pdp1_sbs16.v		pdp1_sbs16.v
pdp1_sbs_decoder.v		pdp1_sbs_decoder.v
pdp1_shrot.v		pdp1_shrot.v
pdp1_shrot_lut.v		pdp1_shrot_lut.v
pdp1_sim.flatptr.v		pdp1_sim.flatptr.v
pdp1_sim.lp.v		pdp1_sim.lp.v
pdp1_skp_decoder.v		pdp1_skp_decoder.v
pdp1_tb.v		pdp1_tb.v
pdp1_write_decoder.v		pdp1_write_decoder.v