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add video ram and make character generation more sophisticated
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13 files changed

+137
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.gitignore

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@@ -20,3 +20,4 @@ jml-8-mini/schematic/*.step
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**/*.FCBak
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**/*.o
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**/*.fs
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**/waveform/*

peripherals/jml-8-mini-vga/src/Makefile

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@@ -16,29 +16,29 @@ all : make_clean toplevel.fs
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# Synthesis
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toplevel.json : $(SRCS)
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@yosys -p "read_verilog $(SRCS); synth_gowin -top toplevel -json toplevel.json"
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yosys -q -p "read_verilog $(SRCS); synth_gowin -top toplevel -json toplevel.json"
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# Place and Route
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toplevel_pnr.json : toplevel.json
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@nextpnr-gowin --json toplevel.json --freq 27 --write \
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nextpnr-gowin -q --json toplevel.json --freq 27 --write \
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toplevel_pnr.json --device ${DEVICE} --family ${FAMILY} \
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--cst ${BOARD}.cst
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# Generate Bitstream
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toplevel.fs : toplevel_pnr.json
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@gowin_pack -d ${FAMILY} -o toplevel.fs toplevel_pnr.json
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gowin_pack -d ${FAMILY} -o toplevel.fs toplevel_pnr.json
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# Programming Board
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program : toplevel.fs
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@openFPGALoader -b ${BOARD} toplevel.fs -f
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openFPGALoader -b ${BOARD} toplevel.fs -f
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# Testing
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%_tb.o : $(TB_DIR)/%_tb.v $(SRCS)
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@iverilog -o $@ -s test $(SRCS) $<
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iverilog -o $@ -s test $(SRCS) $<
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$(WAVE_DIR)/%.vcd : %_tb.o
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@vvp $< -o $@
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vvp $< -o $@
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test : $(WAVES)
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peripherals/jml-8-mini-vga/src/charmem.v

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@@ -0,0 +1,14 @@
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module charrom (
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input [7:0] addr,
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input [2:0] row,
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output [7:0] pixels
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);
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reg [7:0] chars[255:0][7:0];
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initial $readmemh("charrom.txt", chars, 0);
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assign pixels = chars[addr][row];
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endmodule
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@@ -1,8 +1,9 @@
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module chargen (
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input clk,
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input [7:0] character,
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input [2:0] vertcount,
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output pixel
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module pixelgen (
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input clk,
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input [7:0] character,
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input [2:0] vertoffset,
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output pixel
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);
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reg [2:0] index = 0;
@@ -12,10 +13,9 @@ module chargen (
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always @(posedge clk) index <= index + 1;
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charmem #() character_rom (
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.clk(clk),
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charrom #() character_rom (
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.addr(character),
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.row(vertcount[2:0]),
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.row(vertoffset),
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.pixels(pixels)
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);
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peripherals/jml-8-mini-vga/src/testbench/signalgen_tb.v

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@@ -1,7 +1,7 @@
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`timescale 1 ns / 1 ns
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module test ();
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reg clk = 0;
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reg clk = 1;
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wire hsync;
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wire vsync;
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peripherals/jml-8-mini-vga/src/testbench/toplevel_tb.v

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@@ -1,7 +1,7 @@
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`timescale 1 ns / 1 ns
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module test ();
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reg clk = 0;
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reg clk = 1;
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wire hsync;
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wire vsync;
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wire red;

peripherals/jml-8-mini-vga/src/toplevel.v

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@@ -11,7 +11,7 @@ module toplevel (
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wire pixel;
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wire visible;
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reg [7:0] character = 65;
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wire [7:0] character;
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wire [9:0] vertcount;
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wire [9:0] horicount;
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@@ -20,11 +20,6 @@ module toplevel (
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assign blue = pixel;
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assign lum = pixel;
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always @(posedge horicount[2]) begin
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if (character == 65) character <= 32;
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if (character == 32) character <= 65;
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end
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signalgen #() signal_generator (
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.clk(clk),
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.vsync(vsync),
@@ -34,11 +29,18 @@ module toplevel (
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.horicount(horicount)
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);
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chargen #() character_generator (
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pixelgen #() character_generator (
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.clk(clk),
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.character(character),
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.vertcount(vertcount[2:0]),
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.vertoffset(vertcount[2:0]),
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.pixel(pixel)
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);
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videocont #() video_controller (
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.visible (visible),
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.horicount(horicount[9:3]),
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.vertcount(vertcount[8:3]),
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.character(character)
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);
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endmodule
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module videocont (
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input visible,
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input [6:0] horicount,
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input [5:0] vertcount,
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output [7:0] character
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);
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reg [7:0] videoram[59:0][79:0];
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initial $readmemh("videoram.txt", videoram, 0);
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assign character = visible ? videoram[vertcount][horicount] : 0;
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endmodule

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