create basic FPGA-based VGA display

Author: jac-oblong

peripherals/jml-8-mini-vga/src/Makefile

@@ -0,0 +1,60 @@
+BOARD			=		tangnano9k
+FAMILY		=		GW1N-9C
+DEVICE		=		GW1NR-LV9QN88PC6/I5
+
+SRC_DIR		=		.
+TB_DIR		=		testbench
+WAVE_DIR	=		waveform
+
+SRCS			=		$(wildcard $(SRC_DIR)/*.v)
+TESTS			=		$(wildcard $(TB_DIR)/*_tb.v)
+TEST_OBJS	=		$(TESTS:$(TB_DIR)/%_tb.v=%_tb.o)
+WAVES			=		$(TESTS:$(TB_DIR)/%_tb.v=$(WAVE_DIR)/%.vcd)
+
+
+all : make_clean toplevel.fs
+
+# Synthesis
+toplevel.json : $(SRCS)
+	@yosys -p "read_verilog $(SRCS); synth_gowin -top toplevel -json toplevel.json"
+
+# Place and Route
+toplevel_pnr.json : toplevel.json
+	@nextpnr-gowin --json toplevel.json --freq 27 --write \
+		toplevel_pnr.json --device ${DEVICE} --family ${FAMILY} \
+		--cst ${BOARD}.cst
+
+# Generate Bitstream
+toplevel.fs : toplevel_pnr.json
+	@gowin_pack -d ${FAMILY} -o toplevel.fs toplevel_pnr.json
+
+# Programming Board
+program : toplevel.fs
+	@openFPGALoader -b ${BOARD} toplevel.fs -f
+
+
+# Testing
+%_tb.o : $(TB_DIR)/%_tb.v $(SRCS)
+	@iverilog -o $@ -s test $(SRCS) $<
+
+$(WAVE_DIR)/%.vcd : %_tb.o
+	@vvp $< -o $@
+
+test : $(WAVES)
+
+
+# Cleanup build artifacts
+clean :
+	rm -f ./*.fs
+	rm -f ./*.o
+	rm -f ./*.json
+	rm -f ./*.vcd
+	rm -f waveform/*
+
+make_clean :
+	@rm -f ./*.fs
+	@rm -f ./*.o
+	@rm -f ./*.json
+
+.PHONY: clean program test make_clean
+.INTERMEDIATE: toplevel.json toplevel_pnr.json $(TEST_OBJS)

peripherals/jml-8-mini-vga/src/signalgen.v

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+// generates signal timing for VGA 640x480 60Hz standard (25.175MHz clock)
+// also puts red/green/blue/luminence in high impedance state
+
+module signalgen (
+    input clk,
+
+    output vsync,
+    output hsync
+);
+
+   reg [9:0] vertical_count = 0;
+   reg [9:0] horizontal_count = 0;
+
+   assign hsync = (horizontal_count < 656 || horizontal_count >= 752);
+   assign vsync = (vertical_count < 490 || vertical_count >= 492);
+
+   always @(posedge clk) begin
+      if (horizontal_count == 799) begin
+         horizontal_count <= 0;
+         if (vertical_count == 524) vertical_count <= 0;
+         else vertical_count <= vertical_count + 1;
+      end else horizontal_count <= horizontal_count + 1;
+   end
+
+endmodule

peripherals/jml-8-mini-vga/src/tangnano9k.cst

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+IO_LOC "clk" 33;
+
+IO_LOC "vsync" 25;
+IO_LOC "hsync" 26;
+
+IO_LOC "red" 27;
+IO_LOC "green" 28;
+IO_LOC "blue" 29;
+IO_LOC "lum" 30;

peripherals/jml-8-mini-vga/src/testbench/signalgen_tb.v

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+`timescale 1 ns / 1 ns
+
+module test ();
+   reg  clk = 0;
+   wire hsync;
+   wire vsync;
+
+   signalgen #() signal_generator (
+       .clk  (clk),
+       .vsync(vsync),
+       .hsync(hsync)
+   );
+
+   always begin
+      #1 clk = ~clk;
+   end
+
+   initial begin
+      $dumpfile("waveform/signalgen.vcd");
+      $dumpvars(0, test);
+   end
+
+   initial begin
+      #1000000 $finish;
+   end
+
+endmodule

peripherals/jml-8-mini-vga/src/testbench/toplevel_tb.v

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+`timescale 1 ns / 1 ns
+
+module test ();
+   reg  clk = 0;
+   wire hsync;
+   wire vsync;
+   wire red;
+   wire green;
+   wire blue;
+   wire lum;
+
+   toplevel #() t (
+       .clk  (clk),
+       .vsync(vsync),
+       .hsync(hsync),
+       .red  (red),
+       .green(green),
+       .blue (blue),
+       .lum  (lum)
+   );
+
+   always begin
+      #1 clk = ~clk;
+   end
+
+   initial begin
+      $dumpfile("waveform/toplevel.vcd");
+      $dumpvars(0, test);
+   end
+
+   initial begin
+      #1000000 $finish;
+   end
+
+endmodule

peripherals/jml-8-mini-vga/src/toplevel.v

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+module toplevel (
+    input clk,
+
+    output vsync,
+    output hsync,
+    output red,
+    output green,
+    output blue,
+    output lum
+);
+
+   reg [9:0] hori_counter = 0;
+   reg [5:0] quart_counter = 0;
+   reg [3:0] counter = 0;
+
+   always @(posedge clk) begin
+      if (hori_counter == 799) begin
+         hori_counter <= 0;
+         quart_counter <= 0;
+         counter <= 0;
+      end else begin
+         hori_counter <= hori_counter + 1;
+         if (quart_counter == 39) begin
+            quart_counter <= 0;
+            counter <= counter + 1;
+         end else quart_counter <= quart_counter + 1;
+      end
+   end
+
+   assign red   = counter[0] ? counter[0] : 1'bZ;
+   assign green = counter[1] ? counter[1] : 1'bZ;
+   assign blue  = counter[2] ? counter[2] : 1'bZ;
+   assign lum   = counter[3] ? counter[3] : 1'bZ;
+
+   signalgen #() signal_generator (
+       .clk  (clk),
+       .vsync(vsync),
+       .hsync(hsync)
+   );
+
+endmodule