SOF: fix imx8m compilation with IPC4

Signed-off-by: Iuliana Prodan <[email protected]>

Author: iuliana-prodan

src/audio/base_fw.c

@@ -141,9 +141,13 @@ static int basefw_hw_config(uint32_t *data_offset, char *data)
 	tlv_value_uint32_set(tuple, IPC4_HP_EBB_COUNT_HW_CFG, PLATFORM_HPSRAM_EBB_COUNT);
 
 	tuple = tlv_next(tuple);
+#ifdef CONFIG_IMX
+	value =  DAI_NUM_SAI_BASE;
+#else
 	/* 2 DMIC dais */
 	value =  DAI_NUM_SSP_BASE + DAI_NUM_HDA_IN + DAI_NUM_HDA_OUT +
 			DAI_NUM_ALH_BI_DIR_LINKS + 2;
+#endif
 	tlv_value_uint32_set(tuple, IPC4_GATEWAY_COUNT_HW_CFG, value);
 
 	tuple = tlv_next(tuple);

src/audio/copier/copier_dai.c

@@ -186,6 +186,7 @@ int copier_dai_create(struct comp_dev *dev, struct copier_data *cd,
 		dai.is_config_blob = true;
 		type = ipc4_gtw_alh;
 
+#ifndef CONFIG_IMX
 		/* copier
 		 * {
 		 *  gtw_cfg
@@ -225,6 +226,7 @@ int copier_dai_create(struct comp_dev *dev, struct copier_data *cd,
 		} else {
 			dai_index[dai_count - 1] = IPC4_ALH_DAI_INDEX(node_id.f.v_index);
 		}
+#endif
 
 		break;
 	case ipc4_dmic_link_input_class:

src/audio/dai-legacy.c

@@ -90,6 +90,19 @@ int dai_assign_group(struct dai_data *dd, struct comp_dev *dev, uint32_t group_i
 	return 0;
 }
 #endif
+
+int dai_zephyr_multi_endpoint_copy(struct dai_data **dd, struct comp_dev *dev,
+				   struct comp_buffer *multi_endpoint_buffer,
+				   int num_endpoints)
+{
+	return 0;
+}
+
+int dai_zephyr_unbind(struct dai_data *dd, struct comp_dev *dev, void *data)
+{
+	return 0;
+}
+
 /* this is called by DMA driver every time descriptor has completed */
 static void dai_dma_cb(void *arg, enum notify_id type, void *data)
 {

src/include/sof/drivers/alh.h

@@ -8,7 +8,6 @@
 #define __SOF_DRIVERS_ALH__
 
 #include <ipc/dai-intel.h>
-#include <platform/drivers/alh.h>
 #include <sof/lib/dai.h>
 
 struct alh_pdata {

src/ipc/ipc4/dai.c

@@ -11,6 +11,7 @@
 #include <sof/audio/ipc-config.h>
 #include <sof/common.h>
 #include <sof/drivers/alh.h>
+#include <sof/drivers/edma.h>
 #include <rtos/idc.h>
 #include <rtos/alloc.h>
 #include <sof/lib/dai.h>
@@ -71,6 +72,7 @@ int dai_config_dma_channel(struct dai_data *dd, struct comp_dev *dev, const void
 	const struct ipc4_copier_module_cfg *copier_cfg = spec_config;
 	struct ipc_config_dai *dai = &dd->ipc_config;
 	int channel;
+	int handshake;
 
 	switch (dai->type) {
 	case SOF_DAI_INTEL_SSP:
@@ -91,6 +93,17 @@ int dai_config_dma_channel(struct dai_data *dd, struct comp_dev *dev, const void
 		 */
 		channel = 0;
 		break;
+	case SOF_DAI_IMX_SAI:
+		COMPILER_FALLTHROUGH;
+	case SOF_DAI_IMX_ESAI:
+		handshake = dai_get_handshake(dd->dai, dai->direction,
+					      dd->stream_id);
+		channel = EDMA_HS_GET_CHAN(handshake);
+		break;
+	case SOF_DAI_IMX_MICFIL:
+		channel = dai_get_handshake(dd->dai, dai->direction,
+					    dd->stream_id);
+		break;
 	default:
 		/* other types of DAIs not handled for now */
 		comp_err(dev, "dai_config_dma_channel(): Unknown dai type %d", dai->type);
@@ -157,6 +170,11 @@ int ipc_dai_data_config(struct dai_data *dd, struct comp_dev *dev)
 			 dev->ipc_config.frame_fmt, dd->stream_id);
 
 		break;
+	case SOF_DAI_IMX_MICFIL:
+	case SOF_DAI_IMX_SAI:
+	case SOF_DAI_IMX_ESAI:
+		dd->config.burst_elems = dai_get_fifo_depth(dd->dai, dai->direction);
+		break;
 	default:
 		/* other types of DAIs not handled for now */
 		comp_warn(dev, "dai_data_config(): Unknown dai type %d", dai->type);

src/ipc/ipc4/helper.c

@@ -661,10 +661,12 @@ int ipc_comp_disconnect(struct ipc *ipc, ipc_pipe_comp_connect *_connect)
  */
 static inline int process_dma_index(uint32_t dma_id, uint32_t *dir, uint32_t *chan)
 {
+#ifndef CONFIG_IMX
 	if (dma_id > DAI_NUM_HDA_OUT + DAI_NUM_HDA_IN) {
 		tr_err(&ipc_tr, "dma id %d is out of range", dma_id);
 		return IPC4_INVALID_NODE_ID;
 	}
+#endif
 
 	if (dma_id >= PLATFORM_MAX_DMA_CHAN) {
 		*dir = SOF_IPC_STREAM_CAPTURE;

src/platform/imx8m/include/platform/lib/clk.h

@@ -18,6 +18,8 @@ struct sof;
 
 #define CPU_DEFAULT_IDX		0
 
+#define CPU_LOWEST_FREQ_IDX	CPU_DEFAULT_IDX
+
 #define CLK_DEFAULT_CPU_HZ	800000000
 #define CLK_MAX_CPU_HZ		800000000
 

src/platform/imx8m/include/platform/lib/dai.h

@@ -10,6 +10,9 @@
 #ifndef __PLATFORM_LIB_DAI_H__
 #define __PLATFORM_LIB_DAI_H__
 
+/** \brief Number of 'base' SAI ports available */
+#define DAI_NUM_SAI_BASE	6
+
 #endif /* __PLATFORM_LIB_DAI_H__ */
 
 #else

src/platform/imx8m/include/platform/lib/mailbox.h

@@ -14,8 +14,11 @@
 #include <stddef.h>
 #include <stdint.h>
 
+#include <rtos/panic.h>
+#include <rtos/string.h>
+
 /*
- * The Window Region on i.MX8 SRAM is organised like this :-
+ * The Window Region on i.MX8 SRAM is organized like this :-
  * +--------------------------------------------------------------------------+
  * | Offset              | Region         |  Size                             |
  * +---------------------+----------------+-----------------------------------+
@@ -53,6 +56,9 @@
 #define MAILBOX_STREAM_BASE		SRAM_STREAM_BASE
 #define MAILBOX_STREAM_OFFSET		SRAM_STREAM_OFFSET
 
+#define MAILBOX_SW_REG_SIZE		MAILBOX_DEBUG_SIZE
+#define MAILBOX_SW_REG_BASE		MAILBOX_DEBUG_BASE
+
 static inline void mailbox_sw_reg_write(size_t offset, uint32_t src)
 {
 	volatile uint32_t *ptr;
@@ -61,6 +67,37 @@ static inline void mailbox_sw_reg_write(size_t offset, uint32_t src)
 	*ptr = src;
 }
 
+static inline uint32_t mailbox_sw_reg_read(size_t offset)
+{
+	volatile uint32_t *ptr;
+	volatile uint32_t __sparse_cache *ptr_c;
+
+	ptr_c = (volatile uint32_t __sparse_cache *)(MAILBOX_SW_REG_BASE + offset);
+	ptr = cache_to_uncache((uint32_t __sparse_cache *)ptr_c);
+
+	return *ptr;
+}
+
+static inline uint64_t mailbox_sw_reg_read64(size_t offset)
+{
+	volatile uint64_t *ptr;
+	volatile uint64_t __sparse_cache *ptr_c;
+
+	ptr_c = (volatile uint64_t __sparse_cache *)(MAILBOX_SW_REG_BASE + offset);
+	ptr = cache_to_uncache((uint64_t __sparse_cache *)ptr_c);
+
+	return *ptr;
+}
+
+static inline void mailbox_sw_regs_write(size_t offset, const void *src, size_t bytes)
+{
+	int regs_write_err __unused = memcpy_s((void *)(MAILBOX_SW_REG_BASE + offset),
+					       MAILBOX_SW_REG_SIZE - offset, src, bytes);
+
+	assert(!regs_write_err);
+	dcache_writeback_region((__sparse_force void __sparse_cache *)(MAILBOX_SW_REG_BASE +
+								       offset), bytes);
+}
 #endif /* __PLATFORM_LIB_MAILBOX_H__ */
 
 #else

src/platform/imx8m/include/platform/lib/memory.h

@@ -15,6 +15,15 @@
 /* data cache line alignment */
 #define PLATFORM_DCACHE_ALIGN	32
 
+/* Size of a single memory bank (EBB) in bytes */
+#define SRAM_BANK_SIZE (64 * 1024)
+/* Number of memory banks (EBB) */
+#define EBB_BANKS_IN_SEGMENT	32
+/* Number of High Power SRAM memory banks manageable by DSP */
+#define PLATFORM_HPSRAM_EBB_COUNT	0
+/* Number of Low Power SRAM memory banks manageable by DSP */
+#define PLATFORM_LPSRAM_EBB_COUNT	0
+
 /* physical DSP addresses */
 
 #define IRAM_BASE	0x3b6f8000

src/platform/imx8m/include/platform/platform.h

@@ -20,6 +20,9 @@
 struct ll_schedule_domain;
 struct timer;
 
+/* Version of hw implemented by FW (from ROMInfo) */
+#define HW_CFG_VERSION		0
+
 #define PLATFORM_DEFAULT_CLOCK CLK_CPU(0)
 #define LPSRAM_SIZE 16384