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It's legal in SystemVerilog for an assignment to be a swizzle:
assign {a, b} = {c, d};
Currently ROHD will create an intermediate signal for logic nets, rather than do it in a single net_connect line.
net_connect
Enable the ROHD SystemVerilog generation to merge assignments between swizzles.
No response
The text was updated successfully, but these errors were encountered:
LogicNet
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Motivation
It's legal in SystemVerilog for an assignment to be a swizzle:
Currently ROHD will create an intermediate signal for logic nets, rather than do it in a single
net_connect
line.Desired solution
Enable the ROHD SystemVerilog generation to merge assignments between swizzles.
Alternatives considered
No response
Additional details
No response
The text was updated successfully, but these errors were encountered: