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erasure_code: add prefetch and vsetvli optimization Continous integration #337: Pull request #351 synchronize by lvshuo2016
55m 4s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
55m 4s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #336: Pull request #350 synchronize by yinlenree
39s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
39s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #335: Pull request #350 synchronize by yinlenree
39s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
39s
erasure_code: add prefetch and vsetvli optimization Continous integration #334: Pull request #351 opened by lvshuo2016
1m 38s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
1m 38s
cmake: add functional tests Continous integration #333: Commit 5e90721 pushed by pablodelara
46m 37s master
master
46m 37s
Optimize instruction scheduling in gf_*vect_dot_prod_neon Continous integration #332: Pull request #349 synchronize by AWSjswinney
44m 2s AWSjswinney:jswinney/2025-07-21-scheduling-cleanup
AWSjswinney:jswinney/2025-07-21-scheduling-cleanup
44m 2s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #331: Pull request #350 synchronize by yinlenree
1h 3m 26s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
1h 3m 26s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #330: Pull request #350 opened by yinlenree
41s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
41s
Optimize instruction scheduling in gf_*vect_dot_prod_neon Continous integration #329: Pull request #349 opened by AWSjswinney
1m 58s AWSjswinney:jswinney/2025-07-21-scheduling-cleanup
AWSjswinney:jswinney/2025-07-21-scheduling-cleanup
1m 58s
aarch64: Use NEON when SVE width is 128 bits Continous integration #328: Pull request #338 synchronize by AWSjswinney
41m 33s AWSjswinney:master
AWSjswinney:master
41m 33s
aarch64: Use NEON when SVE width is 128 bits Continous integration #327: Pull request #338 synchronize by AWSjswinney
44m 10s AWSjswinney:master
AWSjswinney:master
44m 10s
aarch64: Use NEON when SVE width is 128 bits Continous integration #325: Pull request #338 synchronize by AWSjswinney
44s AWSjswinney:master
AWSjswinney:master
44s
erasure_code: optimize RVV implementation Continous integration #323: Commit d414b27 pushed by pablodelara
41m 14s master
master
41m 14s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #322: Pull request #331 synchronize by lvshuo2016
46m 48s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
46m 48s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #321: Pull request #331 synchronize by lvshuo2016
47m 15s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
47m 15s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #320: Pull request #331 synchronize by lvshuo2016
56m 57s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
56m 57s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #319: Pull request #331 synchronize by lvshuo2016
40m 58s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
40m 58s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #318: Pull request #331 synchronize by lvshuo2016
23m 25s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
23m 25s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #317: Pull request #331 synchronize by lvshuo2016
13m 30s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
13m 30s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #316: Pull request #331 synchronize by lvshuo2016
14m 6s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
14m 6s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #315: Pull request #331 synchronize by lvshuo2016
42m 37s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
42m 37s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #313: Pull request #331 synchronize by lvshuo2016
52m 50s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
52m 50s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #312: Pull request #331 synchronize by lvshuo2016
41m 42s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
41m 42s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #311: Pull request #331 synchronize by lvshuo2016
40m 6s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
40m 6s
The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table, resulting in a performance improvement of over 10 times compared to the existing implementation. Continous integration #310: Pull request #331 synchronize by lvshuo2016
1m 18s lvshuo2016:ec-vector-branch
lvshuo2016:ec-vector-branch
1m 18s