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goldentop
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goldentop
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//--------------------------------------------------------------------------//
// Title: golden_top.v //
// Rev: Rev 5 //
//--------------------------------------------------------------------------//
// Description: All Cyclone V GT Pro Dev Kit I/O signals and settings //
// such as termination, drive strength, etc... //
// Some toggle_rate=0 where needed for fitter rules. (TR=0) //
//--------------------------------------------------------------------------//
// Revision History: //
// Rev 1: First-cut //
// Rev 2: Removed ENET_RX_P/N, ENET_TX_P/N (no SGMII). Put USER_LED //
// 1,5,6,7 into those pins. Corrected hsma_dqs assignments. //
// Removed fm_a[0], fixed flash_advn assignments. Assigned //
// sdi_clk148_up/dn. Fixed ddr3a_clk_p/n assignments. Added //
// clkinbot_p/n. Remove sma_clk_p/n. Added ddr3b_clk_p/n. //
// Moved ddr3b_a[1:0]. Changed Diff SSTL to 2x SSTL15 for DDR //
// clocks and DQS (need IP otherwise). Added hsma_clk_in0, //
// hsma_clk_in0, hsma_clk_out_n1, hsma_clk_out_n2 back in. //
// CKP 20121029 //
// Rev 3: Corrected ddr3a_hmc_gnd assignments. Removed SGMII assg's. //
// Removed hsma_qvld, sma_clk_, user_dipsw[7:6] assg's. Removed//
// hsma_addr_cmd[1] //
// Rev 4: Swapped HSMA and HSMB. Removed SDI_B. Matched with FPGA //
// pinout as of 12/17. //
// Rev 5: Added extra pin for SPI LCD 3/8/13 //
//----------------------------------------------------------------------------
//------ 1 ------- 2 ------- 3 ------- 4 ------- 5 ------- 6 ------- 7 ------7
//------ 0 ------- 0 ------- 0 ------- 0 ------- 0 ------- 0 ------- 0 ------8
//----------------------------------------------------------------------------
//Copyright 2012 Altera Corporation. All rights reserved. Altera products
//are protected under numerous U.S. and foreign patents, maskwork rights,
//copyrights and other intellectual property laws.
//
//This reference design file, and your use thereof, is subject to and
//governed by the terms and conditions of the applicable Altera Reference
//Design License Agreement. By using this reference design file, you
//indicate your acceptance of such terms and conditions between you and
//Altera Corporation. In the event that you do not agree with such terms and
//conditions, you may not use the reference design file. Please promptly
//destroy any copies you have made.
//
//This reference design file being provided on an "as-is" basis and as an
//accommodation and therefore all warranties, representations or guarantees
//of any kind (whether express, implied or statutory) including, without
//limitation, warranties of merchantability, non-infringement, or fitness for
//a particular purpose, are specifically disclaimed. By making this
//reference design file available, Altera expressly does not recommend,
//suggest or require that this reference design file be used in combination
//with any other product not provided by Altera.
//`define DDR3A
//`define DDR3B
//`define USB
//`define FM
//`define ETHERNET
//`define HSMA
//`define HSMB
//`define LCD
`define USER
//`define PCIE
//`define SDIA
//`define SEC
module c5gt_pro_goldentop
(
//GPLL-CLK-----------------------------//8 pins //------------------------
// input clkin_50, //1.8V //50 MHz.
// input clkintop_p, //LVDS //clkintop
// input clkinbot_p, //LVDS //clkinbot
input clkin_r_p, //LVDS //100 MHz prog osc
input clk_125m_p, //LVDS //125 MHz GPLL-req's External Term.
// output sma_clkout, //V // sma_clkout.
// input clk_148_p, //Default 148.5MHz Si571
`ifdef USER
//User-IO------------------------------//28 pins //--------------------------
input [7:0] user_dipsw, //2.5V //User DIP Switches (TR=0)
output [7:0] user_led, //2.5V //Green User LEDs
// input [2:0] user_pb, //2.5V //User Pushbuttons (TR=0)
input cpu_resetn, //2.5V //CPU Reset Pushbutton (TR=0)
`endif
//DVI card output
output [23:0]out_vid_data,
output out_vid_datavalid,
output out_vid_v_sync,
output out_vid_h_sync,
output out_idckp,
output out_dvi_dat,
output out_dvi_clk,
output out_dvi_pd,
output out_dvi_dken,
output out_dvi_ctl1,
output out_dvi_ctl2,
output out_dvi_ctl3,
output out_idckn,
output out_dvi_isel
);
reg regled;
wire out_underflow;
wire clock137;
wire locked;
assign user_led[0] = out_underflow;
assign out_idckp = clock137;
assign out_dvi_dat = 1'b1;
assign out_dvi_clk = 1'b1;
assign out_dvi_pd = 1'b1;
assign out_dvi_dken= 1'b0;
assign out_dvi_ctl1= 1'b0;
assign out_dvi_ctl2= 1'b0;
assign out_dvi_ctl3= 1'b0;
assign out_idckn = 1'b0;
assign out_dvi_isel= 1'b0;
pll_1 pll1 (
.refclk(clkin_r_p), // refclk.clk
.rst(~cpu_resetn), // reset.reset
.outclk_0(clock137), // outclk0.clk
.locked (locked) // locked.export
);
pattern pattern1 (
.clk_clk(clock137), // clk.clk
.reset_reset_n(cpu_resetn), // reset.reset_n
.video_out_vid_clk(clock137), // video_out.vid_clk
.video_out_vid_data(out_vid_data), // .vid_data
.video_out_underflow(out_underflow), // .underflow
.video_out_vid_datavalid(out_vid_datavalid), // .vid_datavalid
.video_out_vid_v_sync(out_vid_v_sync), // .vid_v_sync
.video_out_vid_h_sync(out_vid_h_sync), // .vid_h_sync
.video_out_vid_f(), // .vid_f
.video_out_vid_h(), // .vid_h
.video_out_vid_v() // .vid_v
);
//always @(posedge clock137) begin
// regled = user_dipsw[7];
//end
//
//assign user_led[7] = regled;
endmodule