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cuda_kmeans.ptx
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//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-19856038
// Cuda compilation tools, release 7.5, V7.5.17
// Based on LLVM 3.4svn
//
.version 4.3
.target sm_20
.address_size 64
.extern .shared .align 1 .b8 sharedMemory[];
.extern .shared .align 4 .b8 intermediates[];
.entry _Z20find_nearest_clusteriiiPfS_PiS0_(
.param .u32 _Z20find_nearest_clusteriiiPfS_PiS0__param_0,
.param .u32 _Z20find_nearest_clusteriiiPfS_PiS0__param_1,
.param .u32 _Z20find_nearest_clusteriiiPfS_PiS0__param_2,
.param .u64 _Z20find_nearest_clusteriiiPfS_PiS0__param_3,
.param .u64 _Z20find_nearest_clusteriiiPfS_PiS0__param_4,
.param .u64 _Z20find_nearest_clusteriiiPfS_PiS0__param_5,
.param .u64 _Z20find_nearest_clusteriiiPfS_PiS0__param_6
)
{
.reg .pred %p<16>;
.reg .b16 %rs<3>;
.reg .f32 %f<27>;
.reg .b32 %r<53>;
.reg .b64 %rd<27>;
ld.param.u32 %r19, [_Z20find_nearest_clusteriiiPfS_PiS0__param_0];
ld.param.u32 %r20, [_Z20find_nearest_clusteriiiPfS_PiS0__param_1];
ld.param.u32 %r21, [_Z20find_nearest_clusteriiiPfS_PiS0__param_2];
ld.param.u64 %rd7, [_Z20find_nearest_clusteriiiPfS_PiS0__param_3];
ld.param.u64 %rd8, [_Z20find_nearest_clusteriiiPfS_PiS0__param_4];
ld.param.u64 %rd5, [_Z20find_nearest_clusteriiiPfS_PiS0__param_5];
ld.param.u64 %rd6, [_Z20find_nearest_clusteriiiPfS_PiS0__param_6];
cvta.to.global.u64 %rd1, %rd8;
cvta.to.global.u64 %rd2, %rd7;
mov.u32 %r1, %tid.x;
cvt.u64.u32 %rd9, %r1;
mov.u64 %rd10, sharedMemory;
add.s64 %rd3, %rd10, %rd9;
mov.u16 %rs1, 0;
st.shared.u8 [%rd3], %rs1;
mov.u32 %r22, %ctaid.x;
mov.u32 %r23, %ntid.x;
mad.lo.s32 %r2, %r22, %r23, %r1;
setp.ge.s32 %p1, %r2, %r20;
@%p1 bra BB0_18;
mov.f32 %f24, 0f00000000;
mov.u32 %r43, 0;
mov.f32 %f25, %f24;
setp.lt.s32 %p2, %r19, 1;
@%p2 bra BB0_3;
BB0_2:
mad.lo.s32 %r25, %r43, %r20, %r2;
mul.wide.s32 %rd11, %r25, 4;
add.s64 %rd12, %rd2, %rd11;
mul.lo.s32 %r26, %r43, %r21;
mul.wide.s32 %rd13, %r26, 4;
add.s64 %rd14, %rd1, %rd13;
ld.global.f32 %f12, [%rd14];
ld.global.f32 %f13, [%rd12];
sub.f32 %f14, %f13, %f12;
fma.rn.f32 %f25, %f14, %f14, %f25;
add.s32 %r43, %r43, 1;
setp.lt.s32 %p3, %r43, %r19;
mov.f32 %f24, %f25;
@%p3 bra BB0_2;
BB0_3:
mov.f32 %f22, %f24;
mov.u32 %r49, 0;
setp.lt.s32 %p4, %r21, 2;
@%p4 bra BB0_10;
setp.gt.s32 %p5, %r19, 0;
mov.u32 %r51, 0;
mov.u32 %r44, 1;
mov.u32 %r50, %r51;
mov.u32 %r45, %r44;
@%p5 bra BB0_7;
bra.uni BB0_5;
BB0_7:
mov.u32 %r46, 0;
mov.f32 %f26, 0f00000000;
BB0_8:
mad.lo.s32 %r33, %r46, %r20, %r2;
mul.wide.s32 %rd15, %r33, 4;
add.s64 %rd16, %rd2, %rd15;
mad.lo.s32 %r34, %r46, %r21, %r45;
mul.wide.s32 %rd17, %r34, 4;
add.s64 %rd18, %rd1, %rd17;
ld.global.f32 %f16, [%rd18];
ld.global.f32 %f17, [%rd16];
sub.f32 %f18, %f17, %f16;
fma.rn.f32 %f26, %f18, %f18, %f26;
add.s32 %r46, %r46, 1;
setp.lt.s32 %p8, %r46, %r19;
@%p8 bra BB0_8;
setp.lt.f32 %p9, %f26, %f22;
selp.b32 %r50, %r45, %r50, %p9;
selp.f32 %f22, %f26, %f22, %p9;
add.s32 %r45, %r45, 1;
setp.lt.s32 %p10, %r45, %r21;
mov.u32 %r49, %r50;
@%p10 bra BB0_7;
bra.uni BB0_10;
BB0_5:
mov.f32 %f23, %f22;
BB0_6:
setp.gt.f32 %p6, %f23, 0f00000000;
selp.b32 %r51, %r44, %r51, %p6;
selp.f32 %f23, 0f00000000, %f23, %p6;
add.s32 %r44, %r44, 1;
setp.lt.s32 %p7, %r44, %r21;
mov.u32 %r49, %r51;
@%p7 bra BB0_6;
BB0_10:
cvta.to.global.u64 %rd19, %rd5;
mul.wide.s32 %rd20, %r2, 4;
add.s64 %rd4, %rd19, %rd20;
ld.global.u32 %r35, [%rd4];
setp.eq.s32 %p11, %r35, %r49;
@%p11 bra BB0_12;
mov.u16 %rs2, 1;
st.shared.u8 [%rd3], %rs2;
BB0_12:
st.global.u32 [%rd4], %r49;
bar.sync 0;
shr.u32 %r52, %r23, 1;
setp.eq.s32 %p12, %r52, 0;
@%p12 bra BB0_16;
BB0_13:
setp.ge.u32 %p13, %r1, %r52;
@%p13 bra BB0_15;
add.s32 %r37, %r52, %r1;
cvt.u64.u32 %rd21, %r37;
add.s64 %rd23, %rd10, %rd21;
ld.shared.u8 %r38, [%rd23];
ld.shared.u8 %r39, [%rd3];
add.s32 %r40, %r39, %r38;
st.shared.u8 [%rd3], %r40;
BB0_15:
bar.sync 0;
shr.u32 %r52, %r52, 1;
setp.ne.s32 %p14, %r52, 0;
@%p14 bra BB0_13;
BB0_16:
setp.ne.s32 %p15, %r1, 0;
@%p15 bra BB0_18;
cvta.to.global.u64 %rd24, %rd6;
ld.shared.u8 %r41, [sharedMemory];
mul.wide.u32 %rd25, %r22, 4;
add.s64 %rd26, %rd24, %rd25;
st.global.u32 [%rd26], %r41;
BB0_18:
ret;
}
.entry _Z13compute_deltaPiii(
.param .u64 _Z13compute_deltaPiii_param_0,
.param .u32 _Z13compute_deltaPiii_param_1,
.param .u32 _Z13compute_deltaPiii_param_2
)
{
.reg .pred %p<6>;
.reg .b32 %r<20>;
.reg .b64 %rd<11>;
ld.param.u64 %rd3, [_Z13compute_deltaPiii_param_0];
ld.param.u32 %r9, [_Z13compute_deltaPiii_param_1];
ld.param.u32 %r7, [_Z13compute_deltaPiii_param_2];
cvta.to.global.u64 %rd1, %rd3;
mov.u32 %r1, %tid.x;
mov.u32 %r18, 0;
setp.ge.u32 %p1, %r1, %r9;
@%p1 bra BB1_2;
mul.wide.u32 %rd4, %r1, 4;
add.s64 %rd5, %rd1, %rd4;
ld.global.u32 %r18, [%rd5];
BB1_2:
mul.wide.u32 %rd6, %r1, 4;
mov.u64 %rd7, intermediates;
add.s64 %rd2, %rd7, %rd6;
st.shared.u32 [%rd2], %r18;
bar.sync 0;
add.s32 %r10, %r7, 1;
setp.lt.u32 %p2, %r10, 3;
@%p2 bra BB1_7;
shr.u32 %r11, %r7, 31;
add.s32 %r12, %r7, %r11;
shr.s32 %r19, %r12, 1;
BB1_4:
setp.ge.u32 %p3, %r1, %r19;
@%p3 bra BB1_6;
add.s32 %r13, %r19, %r1;
mul.wide.u32 %rd8, %r13, 4;
add.s64 %rd10, %rd7, %rd8;
ld.shared.u32 %r14, [%rd2];
ld.shared.u32 %r15, [%rd10];
add.s32 %r16, %r14, %r15;
st.shared.u32 [%rd2], %r16;
BB1_6:
bar.sync 0;
shr.u32 %r19, %r19, 1;
setp.ne.s32 %p4, %r19, 0;
@%p4 bra BB1_4;
BB1_7:
setp.ne.s32 %p5, %r1, 0;
@%p5 bra BB1_9;
ld.shared.u32 %r17, [intermediates];
st.global.u32 [%rd1], %r17;
BB1_9:
ret;
}
.entry _Z7predictiiiPfS_Pi(
.param .u32 _Z7predictiiiPfS_Pi_param_0,
.param .u32 _Z7predictiiiPfS_Pi_param_1,
.param .u32 _Z7predictiiiPfS_Pi_param_2,
.param .u64 _Z7predictiiiPfS_Pi_param_3,
.param .u64 _Z7predictiiiPfS_Pi_param_4,
.param .u64 _Z7predictiiiPfS_Pi_param_5
)
{
.reg .pred %p<11>;
.reg .f32 %f<27>;
.reg .b32 %r<41>;
.reg .b64 %rd<17>;
ld.param.u32 %r15, [_Z7predictiiiPfS_Pi_param_0];
ld.param.u32 %r16, [_Z7predictiiiPfS_Pi_param_1];
ld.param.u32 %r17, [_Z7predictiiiPfS_Pi_param_2];
ld.param.u64 %rd4, [_Z7predictiiiPfS_Pi_param_3];
ld.param.u64 %rd5, [_Z7predictiiiPfS_Pi_param_4];
ld.param.u64 %rd3, [_Z7predictiiiPfS_Pi_param_5];
cvta.to.global.u64 %rd1, %rd5;
cvta.to.global.u64 %rd2, %rd4;
mov.u32 %r18, %ctaid.x;
mov.u32 %r19, %ntid.x;
mov.u32 %r20, %tid.x;
mad.lo.s32 %r1, %r18, %r19, %r20;
setp.ge.s32 %p1, %r1, %r16;
@%p1 bra BB2_11;
mov.f32 %f24, 0f00000000;
mov.u32 %r32, 0;
mov.f32 %f25, %f24;
setp.lt.s32 %p2, %r15, 1;
@%p2 bra BB2_3;
BB2_2:
mad.lo.s32 %r22, %r32, %r16, %r1;
mul.wide.s32 %rd6, %r22, 4;
add.s64 %rd7, %rd2, %rd6;
mul.lo.s32 %r23, %r32, %r17;
mul.wide.s32 %rd8, %r23, 4;
add.s64 %rd9, %rd1, %rd8;
ld.global.f32 %f12, [%rd9];
ld.global.f32 %f13, [%rd7];
sub.f32 %f14, %f13, %f12;
fma.rn.f32 %f25, %f14, %f14, %f25;
add.s32 %r32, %r32, 1;
setp.lt.s32 %p3, %r32, %r15;
mov.f32 %f24, %f25;
@%p3 bra BB2_2;
BB2_3:
mov.f32 %f22, %f24;
mov.u32 %r38, 0;
setp.lt.s32 %p4, %r17, 2;
@%p4 bra BB2_10;
setp.gt.s32 %p5, %r15, 0;
mov.u32 %r40, 0;
mov.u32 %r33, 1;
mov.u32 %r39, %r40;
mov.u32 %r34, %r33;
@%p5 bra BB2_7;
bra.uni BB2_5;
BB2_7:
mov.u32 %r35, 0;
mov.f32 %f26, 0f00000000;
BB2_8:
mad.lo.s32 %r30, %r35, %r16, %r1;
mul.wide.s32 %rd10, %r30, 4;
add.s64 %rd11, %rd2, %rd10;
mad.lo.s32 %r31, %r35, %r17, %r34;
mul.wide.s32 %rd12, %r31, 4;
add.s64 %rd13, %rd1, %rd12;
ld.global.f32 %f16, [%rd13];
ld.global.f32 %f17, [%rd11];
sub.f32 %f18, %f17, %f16;
fma.rn.f32 %f26, %f18, %f18, %f26;
add.s32 %r35, %r35, 1;
setp.lt.s32 %p8, %r35, %r15;
@%p8 bra BB2_8;
setp.lt.f32 %p9, %f26, %f22;
selp.b32 %r39, %r34, %r39, %p9;
selp.f32 %f22, %f26, %f22, %p9;
add.s32 %r34, %r34, 1;
setp.lt.s32 %p10, %r34, %r17;
mov.u32 %r38, %r39;
@%p10 bra BB2_7;
bra.uni BB2_10;
BB2_5:
mov.f32 %f23, %f22;
BB2_6:
setp.gt.f32 %p6, %f23, 0f00000000;
selp.b32 %r40, %r33, %r40, %p6;
selp.f32 %f23, 0f00000000, %f23, %p6;
add.s32 %r33, %r33, 1;
setp.lt.s32 %p7, %r33, %r17;
mov.u32 %r38, %r40;
@%p7 bra BB2_6;
BB2_10:
cvta.to.global.u64 %rd14, %rd3;
mul.wide.s32 %rd15, %r1, 4;
add.s64 %rd16, %rd14, %rd15;
st.global.u32 [%rd16], %r38;
bar.sync 0;
BB2_11:
ret;
}