Something

Author: heimskr

chisel/src/main/scala/why/BoothMultiplier.scala

@@ -38,6 +38,7 @@ class BoothMultiplier extends Module {
 		t := 0.U
 
 		state := sBusy
+		step  := 0.U
 
 		out.bits  := 0.U
 		out.valid := false.B
@@ -53,23 +54,18 @@ class BoothMultiplier extends Module {
 
 		} .elsewhen (step === 1.U) {
 
+			t    := p
+			step := 2.U
+
 			switch (p(1, 0)) {
 				is ("b01".U) {
 					t := p + a
 				}
 				is ("b10".U) {
 					t := p + s
 				}
-				is ("b00".U) {
-					t := p
-				}
-				is ("b11".U) {
-					t := p
-				}
 			}
 
-			step := 2.U
-
 		} .elsewhen (step === 2.U) {
 
 			p := t >> 1

chisel/src/main/scala/why/Bundles.scala

@@ -1,6 +1,7 @@
 package why
 
 import chisel3._
+import chisel3.util._
 
 case class IDBundle() extends Bundle {
 	val opcode = UInt(12.W)
@@ -35,8 +36,7 @@ case class MemoryIO() extends Bundle {
 	val writeIn = Flipped(Valid(UInt(64.W)))
 	val readOut = Decoupled(UInt(64.W))
 	val address = Input(UInt(64.W))
-	/** 0 -> byte, 1 -> quarterword, 2 -> halfword, 3 -> word */
-	val width   = Input(UInt(2.W))
+	val size    = Input(UInt(2.W)) // 0 -> byte, 1 -> quarterword, 2 -> halfword, 3 -> word
 	val busy    = Output(Bool())
 }
 

chisel/src/main/scala/why/ControlState.scala

@@ -14,7 +14,7 @@ object ControlState {
 
 	def count: Int = log2Ceil(all.size)
 	def width = count.W
-	def chiselType() = UInt(width)
+	def chiselType = UInt(width)
 }
 
 // case object sStartup0 extends ControlState(0)

chisel/src/main/scala/why/ControlUnit.scala

@@ -11,7 +11,7 @@ class ControlUnit(memorySize: Int) extends Module {
 		val instructionAddr = Input(UInt(64.W))
 		val aluOut          = Input(SInt(64.W))
 		val decoded         = Input(IDBundle())
-		val state           = Output(ControlState.chiselType())
+		val state           = Output(ControlState.chiselType)
 		val mar             = Output(UInt(64.W))
 		val pcInput         = Output(UInt(64.W)) // Written to the program counter whenever pcWrite is true
 		val pcWrite         = Output(Bool())