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tuner_r82xx.c
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/*
* Rafael Micro R820T/R828D driver
*
* Copyright (C) 2013 Mauro Carvalho Chehab <[email protected]>
* Copyright (C) 2013 Steve Markgraf <[email protected]>
*
* This driver is a heavily modified version of the driver found in the
* Linux kernel:
* http://git.linuxtv.org/linux-2.6.git/history/HEAD:/drivers/media/tuners/r820t.c
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <stdio.h>
#include <string.h>
#ifdef _WIN32
#include <windows.h>
#else
#include <unistd.h>
#include <sys/time.h>
#endif
#include "rtl-sdr.h"
#include "rtlsdr_i2c.h"
#include "tuner_r82xx.h"
#define MHZ(x) ((x)*1000*1000)
#define HF 1
#define VHF 2
#define UHF 3
extern int16_t interpolate(int16_t freq, int size, const int16_t *freqs, const int16_t *gains);
extern int rtlsdr_get_agc_val(void *dev, int *slave_demod);
extern uint16_t rtlsdr_demod_read_reg(rtlsdr_dev_t *dev, uint16_t page, uint16_t addr, uint8_t len);
/*
Read registers
Reg Bitmap Symbol Description
------------------------------------------------------------------------------------
R0 [7:0] CHIP_ID reference check point for read mode: 0x96
0x00
------------------------------------------------------------------------------------
R1 [7:6] 10
0x01 [5:0] ADC Analog-Digital Converter for detector 3
------------------------------------------------------------------------------------
R2 [7] 1
0x02 [6] VCO_LOCK 0: PLL has not locked, 1: PLL has locked
[5:0] VCO_INDICATOR VCO band
000000: min (1.75 GHz), 111111: max (3.6 GHz)
------------------------------------------------------------------------------------
R3 [7:4] RF_INDICATOR Mixer gain
0x03 0: Lowest, 15: Highest
[3:0] LNA gain
0: Lowest, 15: Highest
------------------------------------------------------------------------------------
R4 [5:4] vco_fine_tune
0x04 [3:0] fil_cal_code
------------------------------------------------------------------------------------
*/
/*
Write registers
Reg Bitmap Symbol Description
------------------------------------------------------------------------------------
R0 [7] sw_tfq tracking filter Q enhance
0x00 0: off, 1:on
[6] sw_ltsum ltsum pin out switch
0: off, 1:on
[5:4] pw_ltsum ltsum current
00: highest, 01: high, 10: low, 11: lowest
[3] ltsum lt sum LPF function
0: finger 12, 1: finger 6
[2:0] ltsum lt sum HPF function
000: finger 3
001: finger 7
010: finger 11
011: finger 15
100: finger 11
101: finger 15
110: finger 19
111: finger 23
------------------------------------------------------------------------------------
R1 [7:6] low_gain0 Air LNA, maximum gain feedback low gain
0x01 00: 1.8k, 01: 1.25k, 10: 1.25k, 11: 1k
[5] low_gain LNA low gain
0: off, 1:on
[4] pwd_150 lna impedence 150
0: low gain only, 1: on
[3] more_cap lna low pass (air2) more cap
0: off, 1:on
[2] sel_rfa air in diplexer
0: lna1, 1: lna2
[1] lna_gain lna manual gain lsb(new)
[0] lna_15db_enb lna 1.5db enable
0: off, 1:on
------------------------------------------------------------------------------------
R2 [7] g30_31 g30_31
0x02 0: off, 1: on
[6] vcomp channel filter Q control
1: low Q, 0: high Q
[5] vgacomp_15db vga comp range
0: 3dB, 1: 1.5dB
[4] comp_enb echo compensation
0: off, 1: on
[3] b0_en echo compensation mode
0: 3dB, 1: 1.5dB
[2:0] atten Loop Through attenuation
0~7
------------------------------------------------------------------------------------
R3 [2] sw_res1 pll reference spur reduce
0x03 0: off, 1: on
[1] pw_vcoauto pll vco power auto
0: off, 1: on
[0] cp_ix2 pll cp x 2
0: off, 1: on
------------------------------------------------------------------------------------
R4 [7:6] lt_hp new loop through high pass strength
0x04 00: off, 01: low, 10: low, 11: high
[5:4] lt_att new loop through attenuation
00: off, 01: low, 10: higw, 11: highest
[3:2] pwd150_rf2 airin2 pwd150
00: off, 01: low, 10: low, 11: high
[1:0] pwd150_rf1 airin1 pwd150
00: off, 01: low, 10: low, 11: high
------------------------------------------------------------------------------------
R5 [7:6] LOOP_THROUGH Loop through ON/OFF
0x05 0: on, 1: off
[6] pwd_cable1 Cable1 LNA (R828D pin 2)
0:off, 1:on
[5] pwd_air Air in LNA
0:on, 1:off
[4] LNA_GAIN_MODE LNA gain mode switch
0: auto, 1: manual
[3:0] LNA_GAIN LNA manual gain control
15: max gain, 0: min gain
------------------------------------------------------------------------------------
R6 [7] pwd_pdect_lna LNA power detector (wide band) on/off
0x06 0: on, 1: off
[6] pwd_pdect_mix LNA power detector(narrow band) on/off
0: off, 1: on
[5] FILT_GAIN Filter gain 3db
0:0db, 1:+4db (>4MHz bw) or +8db (<4MHz bw)
[4] v6Mhz Mixer Filter 6MHz function
0: off, 1: on
[3] pwd_cable2 Cable2 LNA (R828D pin 3)
0: off, 1: on
[2:0] PW_LNA LNA power control
000: max, 111: min
------------------------------------------------------------------------------------
R7 [7] IMG_R Mixer Sideband
0x07 0: lower, 1: upper
[6] PWD_MIX Mixer power
0:off, 1:on
[5] PW0_MIX Mixer current control
0:max current, 1:normal current
[4] MIXGAIN_MODE Mixer gain mode
0:manual mode, 1:auto mode
[3:0] MIX_GAIN Mixer manual gain control
0000->min, 1111->max
------------------------------------------------------------------------------------
R8 [7] PWD_AMP Mixer buffer power on/off
0x08 0: off, 1:on
[6] PW0_AMP Mixer buffer current setting
0: high current, 1: low current
[5] 0: Q, 1: I
[4:0] IMR_G Image Gain Adjustment
0: min, 31: max
------------------------------------------------------------------------------------
R9 [7] PWD_IFFILT IF Filter power on/off
0x09 0: filter on, 1: off
[6] PW1_IFFILT IF Filter current
0: high current, 1: low current
[5] 0: Q, 1: I
[4:0] IMR_P Image Phase Adjustment
0: min, 31: max
------------------------------------------------------------------------------------
R10 [7] PWD_FILT Filter power on/off
0x0A 0: channel filter off, 1: on
[6:5] PW_FILT Filter power control
00: highest power, 11: lowest power
[4] FILT_Q channel filter Q control
0: low Q, 1: high Q
[3:0] FILT_CODE Filter bandwidth manual fine tune
0000 Widest, 1111 narrowest
------------------------------------------------------------------------------------
R11 [7:5] FILT_BW Filter bandwidth manual course tune
0x0B 000: widest
010 or 001: middle
111: narrowest
[4] CAL_TRIGGER channel filter auto calibration start triggering
1: start
[3:0] HP_COR High pass filter corner control
0000: highest
1111: lowest
------------------------------------------------------------------------------------
R12 [7] pwd_adc adc power control
0: on, 1: off
0x0C [6] PWD_VGA VGA power control
0: vga power off, 1: vga power on
[5] pw0_vga 0: vga max power, 1: vga min power
[4] VGA_MODE VGA GAIN manual / pin selector
1: IF vga gain controlled by vagc pin
0: IF vga gain controlled by vga_code[3:0]
[3:0] VGA_CODE IF vga manual gain control
0000: -12.0 dB
1111: +40.5 dB; -3.5dB/step
------------------------------------------------------------------------------------
R13 [7:4] LNA_VTHH LNA agc power detector voltage threshold high setting
0x0D 1111: 1.94 V
0000: 0.34 V, ~0.1 V/step
[3:0] LNA_VTHL LNA agc power detector voltage threshold low setting
1111: 1.94 V
0000: 0.34 V, ~0.1 V/step
------------------------------------------------------------------------------------
R14 [7:4] MIX_VTH_H MIXER agc power detector voltage threshold high setting
0x0E 1111: 1.94 V
0000: 0.34 V, ~0.1 V/step
[3:0] MIX_VTH_L MIXER agc power detector voltage threshold low setting
1111: 1.94 V
0000: 0.34 V, ~0.1 V/step
------------------------------------------------------------------------------------
R15 [7] FLT_EXT_WIDEST filter extension widest
0x0F 0: off, 1: on
[6:5] ldo5vh 0: LDO 2.9V, 1:LDO 3.0V
[4] CLK_OUT_ENB Clock out pin control
0: clk output on, 1: off
[3] clk_ring_enb 0: ring pll reference clock on, 1: off
[2] clk_filt_enb 0: channel filter calibration clock off, 1: on
[1] CLK_AGC_ENB AGC clk control
0: internal agc clock on, 1: off
[0] GPIO gpio (R828D pin 1)
0: 0, 1: 1
------------------------------------------------------------------------------------
R16 [7:5] SEL_DIV PLL to Mixer divider number control
0x10 000: mixer in = vco out / 2
001: mixer in = vco out / 4
010: mixer in = vco out / 8
011: mixer in = vco out / 16
100: mixer in = vco out / 32
101: mixer in = vco out / 64
[4] REFDIV PLL Reference frequency Divider
0 -> fref=xtal_freq
1 -> fref=xta_freql / 2 (for Xtal >24MHz)
[3] sw_xtal xtal swing control
0: High, 1: Low
[2] agc_clk_s2 1
[1:0] CAPX Internal xtal cap setting
00->no cap
01->10pF
10->20pF
11->30pF
------------------------------------------------------------------------------------
R17 [7:6] PW_LDO_A PLL analog low drop out regulator switch
0x11 00: off
01: 2.1V
10: 2.0V
11: 1.9V
[5:3] pw_cp charge pump current control
000: 0.7 mA
001: 0.6 mA
010: 0.5 mA
011: 0.4 mA
100: 0.3 mA
101: 0.2 mA
110: 0.1 mA
111: Auto
[2] pwd_bias PLL Divider Power
0: on, 1: off
[1:0] pw_hfd PLL BiasHF
00: 100uA
01: 50uA
10: 200uA
11: 150uA
------------------------------------------------------------------------------------
R18 [7:5] pw_vco VCO Core Power
0x12 000: 0-Max
110: low ... 110: 6-Min
111: 7-OFF
[4] pw_dither sigma delta modulator dither function switch
0: on, 1: off
[3] PW_SDM sigma delta modulator switch
0: Enable frac pll, 1: Disable frac pll
[2:1] offset charge pump offset current
00: No offset
01: 30uA
10: 60uA
11: 90uA
[0] p_0406 CP Reference Voltage
0: 0.4-1.4V
1: 0.4-1.2V
------------------------------------------------------------------------------------
R19 [7] pw_atune PLL Auto Tune Clock
0x13 0: on, 1: off
[6] vco_control VCO state auto/manual control switch
0: auto (VCO autotune)
1: manual (select VCO & VCO bank by sel_vco[5:0])
[5:0] sel_vco VCO bank
000000: min (1.75 GHz), 111111: max (3.6 GHz)
------------------------------------------------------------------------------------
R20 [7:6] SI2C PLL integer divider number input Si2c
0x14 Nint=4*Ni2c+Si2c+13
PLL divider number Ndiv = (Nint + Nfra)*2
[5:0] NI2C PLL integer divider number input Ni2c
------------------------------------------------------------------------------------
R21 [7:0] SDM_IN[8:1] PLL fractional divider number input SDM[16:1]
0x15 Nfra=SDM_IN[16]*2^-1+SDM_IN[15]*2^-2+...
R22 [7:0] SDM_IN[16:9] +SDM_IN[2]*2^-15+SDM_IN[1]*2^-16
0x16
------------------------------------------------------------------------------------
R23 [7:6] PW_LDO_D PLL digital low drop out regulator supply current switch
0x17 00: 1.8V,8mA
01: 1.8V,4mA
10: 2.0V,8mA
11: OFF
[5:4] pw45 prescale 45 current
00: 100uA, 01: 50uA
10: 200u, 11: 150u
[3] OPEN_D Open drain (R828D pin 4)
0: High-Z, 1: Low-Z
[2:1] pw_IQ IQ generator current control
00: Div_min, Buf_min
01: Div_mid, Buf_max
10: Div_mid, Buf_min
11: Div_max, Buf_max
[0] pwd_IQ IQ generator power
0: on, 1: off
------------------------------------------------------------------------------------
R24 [7] pw_ringout RingPLL Test VCO Output Enable
0: off, 1: on
[6] ring_cp_current RingPLL charge pump curren
0: 15u, 1: 150u
[5] ring_div[0] ring_div bit 0
0x18 [4] ring_pwd RingPLL power
0: off, 1:on
[3:0] n_ring RingPLL integer divider number control
ring_vco = (16+n_ring)*8*pll_ref, n_ring = 9...14
------------------------------------------------------------------------------------
R25 [7] PWD_RFFILT RF Filter power
0x19 0: off, 1:on
[6:5] POLYFIL_CUR RF poly filter current
11: min
[4] SW_AGC Switch agc_pin
0:agc=agc_in
1:agc=agc_in2 (R828D Pin 18)
[3:2] ring_pw RingPLL VCO power
00: off, 01: off, 10: min, 11: max
[1:0] ring_div[2:1] cal_freq = ring_vco / divisor
000: ring_freq = ring_vco / 4
001: ring_freq = ring_vco / 6
010: ring_freq = ring_vco / 8
011: ring_freq = ring_vco / 12
100: ring_freq = ring_vco / 16
101: ring_freq = ring_vco / 24
110: ring_freq = ring_vco / 32
111: ring_freq = ring_vco / 48
------------------------------------------------------------------------------------
R26 [7:6] RF_MUX_POLY Tracking Filter switch
0x1A 00: TF on
01: Bypass
[5:4] AGC clk
00: 300ms, 01: 300ms, 10: 80ms, 11: 20ms
[3:2] PLL_AUTO_CLK PLL auto tune clock rate
00: 128 kHz
01: 32 kHz
10: 8 kHz
[1:0] RFFILT RF FILTER to reject 3rd harmonic
00: highest band
01: med band
10: low band
------------------------------------------------------------------------------------
R27 [7:4] TF_NCH 0000 highest corner for LPNF
0x1B 1111 lowest corner for LPNF
[3:0] TF_LP 0000 highest corner for LPF
1111 lowest corner for LPF
------------------------------------------------------------------------------------
R28 [7:4] PDET3_GAIN Power detector 3 (Mixer) TOP(take off point) control
0x1C 0: Highest, 15: Lowest
[3] discharge mode
0: on
[2] pdect_mode LNA power detector mode switch
0: normal, 1: low discharge mode
[1] from_ring Mixer input source select
0: rf in, 1: ring pll in
[0] pwd_vco_out PLL VCO Output Enable
0: OFF, 1: ON
------------------------------------------------------------------------------------
R29 [7:6] dectbw LNA narrow band power detector bw switch
0x1D 0: highest bw, ..., 3: lowest bw
[5:3] PDET1_GAIN Power detector 1 (LNA wide band) TOP(take off point) control
0: Highest, 7: Lowest
[2:0] PDET2_GAIN Power detector 2 (LNA narrow band) TOP(take off point) control
0: Highest, 7: Lowest
------------------------------------------------------------------------------------
R30 [7] sw_pdect det_cap2 input switch
0x1E 0: for mixer AGC operation
1: for ADC readout operation
[6] FILTER_EXT Filter extension under weak signal
0: Disable, 1: Enable
[5] att13_ext channel filter extension start point
0: extension @ LNA max, 1: extension @ LNA max-1
[4:0] PDET_CLK Power detector timing control (LNA discharge current)
11111: max, 00000: min
------------------------------------------------------------------------------------
R31 [7] LT_ATT Loop through attenuation
0x1F 0: Enable, 1: Disable
[6:2] 10000
[1:0] pw_ring
0: -5dB, 1: 0dB, 2: -8dB, 3: -3dB
------------------------------------------------------------------------------------
*/
/*
* Static constants
*/
/* Those initial values start from REG_SHADOW_START */
static uint8_t r82xx_init_array[] = {
0x80, //Reg 0x05
0x12, //Reg 0x06
0x70, //Reg 0x07
0xc0, //Reg 0x08
0x40, //Reg 0x09
0xdb, //Reg 0x0a
0x6b, //Reg 0x0b
0xf0, //Reg 0x0c
0x53, //Reg 0x0d
0x53, //Reg 0x0e
0x68, //Reg 0x0f
0x64, //Reg 0x10
0xbb, //Reg 0x11
0x80, //Reg 0x12
0x00, //Reg 0x13
0x0f, //Reg 0x14
0x00, //Reg 0x15
0xc0, //Reg 0x16
0x30, //Reg 0x17
0x48, //Reg 0x18
0xec, //Reg 0x19
0x60, //Reg 0x1a
0x00, //Reg 0x1b
0x24, //Reg 0x1c
0xdd, //Reg 0x1d
0x0e, //Reg 0x1e
0x40 //Reg 0x1f
};
/* Tuner frequency ranges */
static const struct r82xx_freq_range freq_ranges[] = {
{
/* .freq = */ 0, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
/* .tf_c = */ 0xdf, /* R27[7:0] band2,band0 */
}, {
/* .freq = */ 50, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
/* .tf_c = */ 0xbe, /* R27[7:0] band4,band1 */
}, {
/* .freq = */ 55, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
/* .tf_c = */ 0x8b, /* R27[7:0] band7,band4 */
}, {
/* .freq = */ 60, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
/* .tf_c = */ 0x7b, /* R27[7:0] band8,band4 */
}, {
/* .freq = */ 65, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
/* .tf_c = */ 0x69, /* R27[7:0] band9,band6 */
}, {
/* .freq = */ 70, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
/* .tf_c = */ 0x58, /* R27[7:0] band10,band7 */
}, {
/* .freq = */ 75, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
/* .tf_c = */ 0x44, /* R27[7:0] band11,band11 */
}, {
/* .freq = */ 90, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
/* .tf_c = */ 0x34, /* R27[7:0] band12,band11 */
}, {
/* .freq = */ 100, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x01, /* R26[7:6]=0 (LPF) R26[1:0]=1 (middle) */
/* .tf_c = */ 0x34, /* R27[7:0] band12,band11 */
}, {
/* .freq = */ 110, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x01, /* R26[7:6]=0 (LPF) R26[1:0]=1 (middle) */
/* .tf_c = */ 0x24, /* R27[7:0] band13,band11 */
}, {
/* .freq = */ 140, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x01, /* R26[7:6]=0 (LPF) R26[1:0]=1 (middle) */
/* .tf_c = */ 0x14, /* R27[7:0] band14,band11 */
}, {
/* .freq = */ 174, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x00, /* R26[7:6]=0 (LPF) R26[1:0]=0 (high) */
/* .tf_c = */ 0x12, /* R27[7:0] band14,band13 */
}, {
/* .freq = */ 200, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x00, /* R26[7:6]=0 (LPF) R26[1:0]=0 (high) */
/* .tf_c = */ 0x11, /* R27[7:0] band14,band14 */
}, {
/* .freq = */ 240, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x00, /* R26[7:6]=0 (LPF) R26[1:0]=0 (high) */
/* .tf_c = */ 0x00, /* R27[7:0] highest,highest */
}, {
/* .freq = */ 280, /* Start freq, in MHz */
/* .rf_mux_ploy = */ 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (high) */
/* .tf_c = */ 0x00, /* R27[7:0] highest,highest */
}
};
/*
* I2C read/write code and shadow registers logic
*/
static void shadow_store(struct r82xx_priv *priv, uint8_t reg, const uint8_t *val, int len)
{
if(reg >= NUM_REGS)
return;
if (len <= 0)
return;
if (len > NUM_REGS - reg)
len = NUM_REGS - reg;
memcpy(&priv->regs[reg], val, len);
}
static int r82xx_write(struct r82xx_priv *priv, uint8_t reg, uint8_t *buf, int len)
{
int rc;
/* Store the shadow registers */
shadow_store(priv, reg, buf, len);
rc = rtlsdr_i2c_write_fn(priv->rtl_dev, priv->cfg->i2c_addr, reg, buf, len);
if (rc != len) {
fprintf(stderr, "%s: i2c wr failed=%d reg=%02x len=%d\n",
__FUNCTION__, rc, reg, len);
if (rc < 0)
return rc;
return -1;
}
return 0;
}
static inline int r82xx_write_reg(struct r82xx_priv *priv, uint8_t reg, uint8_t val)
{
return r82xx_write(priv, reg, &val, 1);
}
static int r82xx_read_cache_reg(struct r82xx_priv *priv, int reg)
{
if (reg >= 0 && reg < NUM_REGS)
return priv->regs[reg];
else
return -1;
}
static int r82xx_write_reg_mask(struct r82xx_priv *priv, uint8_t reg, uint8_t val,
uint8_t bit_mask)
{
int rc = r82xx_read_cache_reg(priv, reg);
if (rc < 0)
return rc;
val = (rc & ~bit_mask) | (val & bit_mask);
if(rc == val)
return 0;
else
return r82xx_write(priv, reg, &val, 1);
}
static uint8_t r82xx_bitrev(uint8_t byte)
{
const uint8_t lut[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf };
return (lut[byte & 0xf] << 4) | lut[byte >> 4];
}
static int r82xx_read(struct r82xx_priv *priv, uint8_t *buf, int len)
{
int rc, i;
//up to 16 registers can be read
if(len > 16)
return -1;
rc = rtlsdr_i2c_read_fn(priv->rtl_dev, priv->cfg->i2c_addr, 0, buf, len);
if (rc != len) {
fprintf(stderr, "%s: i2c rd failed=%d len=%d\n",
__FUNCTION__, rc, len);
if (rc < 0)
return rc;
return -1;
}
/* Copy data to the output buffer */
for (i = 0; i < len; i++)
buf[i] = r82xx_bitrev(buf[i]);
return 0;
}
/*static void print_registers(struct r82xx_priv *priv)
{
uint8_t data[5];
int rc;
unsigned int i;
rc = r82xx_read(priv, data, sizeof(data));
if (rc < 0)
return;
for(i=0; i<sizeof(data); i++)
fprintf(stderr, "%02x ", data[i]);
for(i=sizeof(data); i<32; i++)
fprintf(stderr, "%02x ", r82xx_read_cache_reg(priv, i));
fprintf(stderr, "\n");
}*/
//RTL-SDR.COM
static const int16_t abs_freqs_r820t[] = {
25, 26, 27, 28, 30, 32, 35, 40, 50, 50, 55, 55, 60, 60, 65, 65, 70, 70, 75, 75,100,100,140,140,174,174,200,200,240,240,280,280,320,345,345,600,850,1000,1500,1700,1750};
static const int16_t abs_gains_r820t[] = {
194,178,169,161,149,141,134,137,143,139,139,127,127,127,127,118,118,113,114, 90, 92,104,107,107,102, 86, 83, 77, 72, 69, 68, 59, 66, 71, 71, 92,109, 118, 138, 145, 153};
//Astrometa
static const int16_t abs_freqs_r828d[] = {
25, 26, 27, 28, 30, 32, 35, 40, 50, 50, 55, 55, 60, 60, 65, 65, 70, 70, 75, 75,100,100,140,140,174,174,200,200,240,240,260,280,280,320,345,345,365,400,500,600,850,1000,1500,1700,1750};
static const int16_t abs_gains_r828d[] = {
251,245,239,234,224,215,209,202,192,189,184,174,170,170,167,160,157,153,151,130,124,137,125,127,105,100, 90, 89, 92, 84, 87, 98, 93,114,146,129,110, 98, 97, 102,110,121, 187, 230, 241};
//RTL-SDR Blog V4
static const int16_t abs_freqs_rtlsdr_v4[] = {
1, 3, 5, 10, 15, 20, 23, 25, 27, 27, 30, 35, 40, 50, 50, 55, 55, 60, 60, 65, 65, 70, 70, 75, 75, 90, 90,100,100,110,110,120,120,140,140,160,160,174,174,200,220,230,230,240,240,250,250,265,280,280,300,330,360,400,450,500,600,800,1000,1250,1500,1760};
static const int16_t abs_gains_rtlsdr_v4[] = {
210,136,112,101,114,138,169,215,255,167,165,168,168,182,171,170,160,159,160,159,152,152,148,148,126,127,127,128,141,140,141,140,149,129,130,140,126,120,115,114,119,127,114,115,114,119,146,119,109,106, 97, 94, 94, 97,106,115,137,169, 189, 206, 211, 208};
static void calculate_abs_gain(struct r82xx_priv *priv)
{
if (priv->cfg->rafael_chip == CHIP_R828D)
{
if (priv->cfg->xtal > 24000000.0) //RTL-SDR Blog V4
priv->abs_gain = interpolate(priv->freq, ARRAY_SIZE(abs_gains_rtlsdr_v4), abs_freqs_rtlsdr_v4, abs_gains_rtlsdr_v4);
else
priv->abs_gain = interpolate(priv->freq, ARRAY_SIZE(abs_gains_r828d), abs_freqs_r828d, abs_gains_r828d);
}
else
priv->abs_gain = interpolate(priv->freq, ARRAY_SIZE(abs_gains_r820t), abs_freqs_r820t, abs_gains_r820t);
}
/*
* r82xx tuning logic
*/
static int r82xx_set_mux(struct r82xx_priv *priv, uint32_t freq)
{
const struct r82xx_freq_range *range;
int rc;
unsigned int i;
/* Get the proper frequency range */
freq = freq / 1000000;
for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++)
{
if (freq < freq_ranges[i + 1].freq)
break;
}
range = &freq_ranges[i];
/* RF_MUX,Polymux */
rc = r82xx_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
if (rc < 0)
return rc;
/* TF BAND */
rc = r82xx_write_reg(priv, 0x1b, range->tf_c);
return rc;
}
static int r82xx_set_pll(struct r82xx_priv *priv, uint32_t freq)
{
int rc, i;
int64_t vco_freq, vco_div;
uint32_t vco_min = 1770000000;
double pll_ref;
uint32_t sdm;
uint8_t div_num;
uint8_t refdiv2 = 0;
uint8_t ni, si, nint, val;
uint8_t data[3];
if ((freq < 25000000) || (freq > vco_min)){
fprintf(stderr, "[R82XX] No valid PLL values for %u Hz!\n", freq);
return -1;
}
pll_ref = priv->cfg->xtal;
if (priv->cfg->xtal > 24000000.0) {
pll_ref /= 2;
refdiv2 = 0x10;
}
rc = r82xx_write_reg_mask(priv, 0x10, refdiv2, 0x10);
if (rc < 0)
return rc;
/* set pll autotune = 128kHz */
rc = r82xx_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
if (rc < 0)
return rc;
/* set VCO current = 100 */
rc = r82xx_write_reg_mask(priv, 0x12, 0x80, 0xe0);
if (rc < 0)
return rc;
/* Calculate divider */
for (div_num = 0; div_num < 5; div_num++)
if ((freq << (div_num + 1)) >= vco_min)
break;
rc = r82xx_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
if (rc < 0)
return rc;
vco_freq = (int64_t)freq << (div_num + 1);
/*
* We want to approximate:
*
* vco_freq / (2 * pll_ref)
*
* in the form:
*
* nint + sdm/65536
*
* where nint,sdm are integers and 0 < nint, 0 <= sdm < 65536
*
* Scaling to fixed point and rounding:
*
* vco_div = 65536*(nint + sdm/65536) = int( 0.5 + 65536 * vco_freq / (2 * pll_ref) )
* vco_div = 65536*nint + sdm = int( (pll_ref + 65536 * vco_freq) / (2 * pll_ref) )
*/
vco_div = (pll_ref + 65536 * vco_freq) / (2 * pll_ref);
nint = vco_div / 65536;
sdm = vco_div % 65536;
ni = (nint - 13) / 4;
si = nint - 4 * ni - 13;
rc = r82xx_write_reg(priv, 0x14, ni + (si << 6));
if (rc < 0)
return rc;
/* pw_sdm */
if (sdm == 0)
val = 0x08;
else
val = 0x00;
rc = r82xx_write_reg_mask(priv, 0x12, val, 0x08);
if (rc < 0)
return rc;
rc = r82xx_write_reg(priv, 0x16, sdm >> 8);
if (rc < 0)
return rc;
rc = r82xx_write_reg(priv, 0x15, sdm & 0xff);
if (rc < 0)
return rc;
for (i = 0; i < 2; i++) {
/* Check if PLL has locked */
rc = r82xx_read(priv, data, 3);
if (rc < 0)
return rc;
if (data[2] & 0x40)
break;
if (!i) {
/* Didn't lock. Increase VCO current */
rc = r82xx_write_reg_mask(priv, 0x12, 0x60, 0xe0);
if (rc < 0)
return rc;
}
}
if (!(data[2] & 0x40)) {
fprintf(stderr, "[R82XX] PLL not locked for %u Hz!\n", freq);
priv->has_lock = 0;
return -1;
}
priv->has_lock = 1;
/* set pll autotune = 8kHz */
rc = r82xx_write_reg_mask(priv, 0x1a, 0x08, 0x08);
if (rc < 0)
return rc;
{
int zf, tuning_error;
int64_t actual_vco;
double dither_offset = 0.0;
uint8_t mix_div = 1 << (div_num + 1);
if(sdm) //frac pll enabled
{
if(r82xx_read_cache_reg(priv, 0x12) & 0x10)
dither_offset = 0.5;
else
dither_offset = 0.25;
}
actual_vco = 2 * pll_ref * nint + 2 * pll_ref * (dither_offset + sdm) / 65536;
tuning_error = (int)(actual_vco - vco_freq) / mix_div;
//fprintf(stderr, "[R82XX] requested %uHz; selected mix_div=%u vco_freq=%lld nint=%u sdm=%u; actual_vco=%lld; xtal=%.1f, tuning error=%dHz\n",
// freq, mix_div, vco_freq, nint, sdm, actual_vco, priv->cfg->xtal, tuning_error);
if(priv->sideband)
zf = priv->int_freq - tuning_error;
else
zf = priv->int_freq + tuning_error;
return rtlsdr_set_if_freq(priv->rtl_dev, zf+3);
}
}
static int r82xx_sysfreq_sel(struct r82xx_priv *priv,
enum r82xx_tuner_type type)
{
int rc;
if (priv->cfg->use_predetect) {
rc = r82xx_write_reg_mask(priv, 0x06, 0x40, 0x40);
if (rc < 0)
return rc;
}
priv->input = 0;
/*
* Set LNA
*/
if (type != TUNER_ANALOG_TV) {
/* LNA TOP: lowest */
rc = r82xx_write_reg_mask(priv, 0x1d, 0, 0x38);
if (rc < 0)
return rc;
/* 0: PRE_DECT off */
rc = r82xx_write_reg_mask(priv, 0x06, 0, 0x40);
if (rc < 0)
return rc;
/* agc clk 250hz */
rc = r82xx_write_reg_mask(priv, 0x1a, 0x30, 0x30);
if (rc < 0)
return rc;
/* write LNA TOP = 3 */
rc = r82xx_write_reg_mask(priv, 0x1d, 0x18, 0x38);
if (rc < 0)
return rc;
/* agc clk 60hz */
rc = r82xx_write_reg_mask(priv, 0x1a, 0x20, 0x30);
if (rc < 0)
return rc;
} else {
/* PRE_DECT off */
rc = r82xx_write_reg_mask(priv, 0x06, 0, 0x40);
if (rc < 0)
return rc;
/* write LNA TOP */ /* detect bw 3, lna top:4, predet top:2 */
rc = r82xx_write_reg_mask(priv, 0x1d, 0xe5, 0x38);
if (rc < 0)
return rc;
/* agc clk 1Khz, external det1 cap 1u */
rc = r82xx_write_reg_mask(priv, 0x1a, 0x00, 0x30);
if (rc < 0)
return rc;
rc = r82xx_write_reg_mask(priv, 0x10, 0x00, 0x04);
if (rc < 0)
return rc;
}
return 0;
}
int r82xx_set_gain_mode(struct r82xx_priv *priv, int set_manual_gain)
{
return r82xx_write_reg_mask(priv, 0x0c, set_manual_gain ? 0x00 : 0x10, 0x10);
}
static const int r82xx_gains[] = {
0,34,68,102,137,171,207,240,278,312,346,382,416,453,488,527};
int r82xx_set_gain_index(struct r82xx_priv *priv, unsigned int i)
{
return r82xx_write_reg_mask(priv, 0x0c, i, 0x0f);
}
#ifdef DEBUG
static unsigned char cmd = 0;
#endif
/* expose/permit tuner specific i2c register hacking! */
int r82xx_set_i2c_register(struct r82xx_priv *priv, unsigned i2c_register, unsigned data, unsigned mask)
{
#ifdef DEBUG
if(i2c_register == NUM_REGS+REG_SHADOW_START) //Debug register
{
//AGC-Test
if(mask & 1)
{
rtlsdr_set_agc_mode(priv->rtl_dev, data & 1);
fprintf(stderr, "set agc mode %u\n", data & 1);
}
//Reset Demod
if((mask & 2) && (data & 2))
{
rtlsdr_reset_demod(priv->rtl_dev);
fprintf(stderr, "reset demod\n");
}
if((mask & 8) && (data & 8))
{
r82xx_write_reg(priv, 0x05, 0xa0); //LNA off
r82xx_write_reg(priv, 0x07, 0x60); //Mixer minimal gain
r82xx_write_reg(priv, 0x0f, 0x60); //ring clk on
r82xx_write_reg(priv, 0x18, 0x5b); //ring power on
r82xx_write_reg(priv, 0x19, 0xef); //ring_freq = ring_vco / 48
r82xx_write_reg(priv, 0x1c, 0x26); //from ring = ring pll in
}
cmd = (cmd & ~mask) | (data & mask);
return 0;
}
else
{
if(i2c_register >= NUM_REGS)
i2c_register -= NUM_REGS;
return r82xx_write_reg_mask(priv, i2c_register & 0xFF, data & 0xff, mask & 0xff);
}
#endif
if(i2c_register < NUM_REGS)
return r82xx_write_reg_mask(priv, i2c_register & 0xFF, data & 0xff, mask & 0xff);
else
return -1;
}
static const int16_t lna_freqs_r820t[] = {
25, 30, 50, 75, 100, 200, 500, 750, 980,1250,1500,1700};
static const int16_t lna_gains_r820t[][16] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ 36, 36, 35, 35, 35, 35, 33, 30, 29, 28, 30, 30},
{ 77, 76, 74, 74, 74, 74, 70, 66, 65, 64, 69, 68},
{115, 113, 109, 108, 108, 107, 105, 103, 104, 104, 104, 104},
{146, 141, 136, 131, 131, 130, 131, 134, 137, 139, 130, 124},
{160, 155, 150, 147, 146, 145, 146, 149, 152, 154, 147, 142},
{184, 180, 176, 174, 172, 172, 173, 176, 179, 181, 175, 170},
{208, 205, 201, 200, 199, 198, 200, 202, 205, 206, 202, 194},
{234, 231, 228, 227, 226, 226, 229, 231, 233, 230, 227, 215},
{260, 258, 254, 254, 254, 253, 255, 253, 249, 240, 232, 211},
{281, 279, 275, 274, 273, 271, 274, 267, 256, 242, 233, 213},
{293, 291, 287, 286, 284, 282, 288, 278, 263, 246, 236, 215},
{306, 305, 301, 299, 296, 294, 302, 290, 271, 251, 241, 220},
{328, 327, 322, 321, 319, 316, 317, 297, 276, 256, 242, 218},
{345, 343, 339, 338, 337, 334, 334, 317, 296, 272, 252, 225},
{289, 299, 322, 339, 342, 343, 346, 325, 303, 279, 255, 227}};
static const int16_t lna_freqs_r828d[] = {
25, 30, 50, 100, 200, 345, 345, 500, 750, 980,1250,1500,1700};
static const int16_t lna_gains_r828d[][16] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{ 43, 41, 37, 35, 36, 41, 42, 39, 33, 32, 33, 29, 29},
{ 99, 94, 84, 78, 79, 87, 87, 82, 71, 69, 72, 67, 64},
{133, 130, 122, 114, 111, 111, 111, 108, 103, 103, 103, 101, 100},
{146, 147, 148, 139, 130, 117, 120, 121, 123, 128, 119, 117, 124},
{177, 177, 177, 169, 163, 153, 136, 137, 139, 144, 138, 134, 143},
{205, 204, 202, 195, 191, 185, 166, 166, 167, 172, 169, 168, 168},
{232, 231, 227, 221, 219, 216, 196, 195, 195, 200, 201, 196, 189},
{262, 260, 254, 249, 248, 251, 227, 225 ,225, 231, 234, 221, 201},
{293, 290, 281, 277, 278, 286, 258, 255, 252, 253, 248, 217, 191},
{300, 299, 297, 295, 293, 297, 267, 270, 268, 262, 252, 218, 192},
{302, 303, 306, 305, 301, 303, 273, 279, 281, 271, 258, 222, 195},