toolchain fails, when using ISERDESE2 in OVERSAMPLE mode (xc7, arty_a7 35)

[bl0x]

VTR fails with the following message when running the code below:

Error 1: 
Type: Blif file
File: top.eblif
Line: 204
Message: Failed to find matching architecture model for 'ISERDESE2'

I'd be happy to list version information. Is there a concise way to do so for symbiflow?

$ yosys --version
Yosys 0.9+4270 

$ vpr --version
Version: 8.1.0-dev+06317d042
Revision: 8.0.0-4118-g06317d042

$ python --version
Python 3.7.10

Arch defs are: continuous/install/459/20211116-000105/

I found inspiration for the code here:

• naps/../io.py

Minimal (?) example:

#!/usr/bin/env nmigen

from nmigen import *
from nmigen.build import *
from nmigen_boards.arty_a7 import *

class ISERDESE2(Elaboratable):
    def __init__(self):
        self.clk = Signal()
        self.clkb = Signal()
        self.oclk = Signal()
        self.oclkb = Signal()
        self.rst = Signal()
        self.ddly = Signal()
        self.s = Signal(4)
        # unused outputs
        self.q = Signal(8)
        self.o = Signal()
        self.shiftout = Signal(2)

    def elaborate(self, platform):
        m = Module()
        m.submodules += Instance("ISERDESE2",
                p_DATA_RATE="DDR",
                p_DATA_WIDTH=4,
                p_DYN_CLKDIV_INV_EN="FALSE",
                p_DYN_CLK_INV_EN="FALSE",
                p_INIT_Q1=0,
                p_INIT_Q2=0,
                p_INIT_Q3=0,
                p_INIT_Q4=0,
                p_INTERFACE_TYPE="OVERSAMPLE",
                p_IOBDELAY="IFD",
                p_NUM_CE="1",
                p_OFB_USED="FALSE",
                p_SERDES_MODE="MASTER",
                p_SRVAL_Q1=0,
                p_SRVAL_Q2=0,
                p_SRVAL_Q3=0,
                p_SRVAL_Q4=0,
                i_BITSLIP=0,
                i_CE1=1,
                i_CE2=1,
                i_CLK=self.clk,
                i_CLKB=self.clkb,
                i_CLKDIV=0,
                i_CLKDIVP=0,
                i_D=0,
                i_DDLY=self.ddly,
                i_DYNCLKDIVSEL=0,
                i_DYNCLKSEL=0,
                i_OCLK=self.oclk,
                i_OCLKB=self.oclkb,
                i_OFB=0,
                i_RST=self.rst,
                i_SHIFTIN1=0,
                i_SHIFTIN2=0,
                o_O=self.o,
                o_Q1=self.s[0],
                o_Q2=self.s[2],
                o_Q3=self.s[1],
                o_Q4=self.s[3],
                o_Q5=self.q[4],
                o_Q6=self.q[5],
                o_Q7=self.q[6],
                o_Q8=self.q[7],
                o_SHIFTOUT1=self.shiftout[0],
                o_SHIFTOUT2=self.shiftout[1]
                )
        return m

class IserdesTest(Elaboratable):

    def elaborate(self, platform):
        data_in = platform.request('data_in', 1)
        data_out = platform.request('data_out', 1)
        iserdes = ISERDESE2()

        m = Module()
        m.submodules += iserdes

        m.d.comb += [
                iserdes.ddly.eq(data_in.p0),
                data_out.p1.eq(iserdes.s[0]),
                data_out.p2.eq(iserdes.s[1]),
                data_out.p3.eq(iserdes.s[2]),
                data_out.p4.eq(iserdes.s[3])
                ]
        return m

if __name__ == "__main__":
    platform = ArtyA7_35Platform(toolchain="Symbiflow")
    ck_io = ("ck_io", 0)
    platform.add_resources([
        Resource("data_in", 1,
            Subsignal("p0", Pins("io1", conn=ck_io, dir='o'))
            ),
        Resource("data_out", 1,
            Subsignal("p1", Pins("io2", conn=ck_io, dir='o')),
            Subsignal("p2", Pins("io3", conn=ck_io, dir='o')),
            Subsignal("p3", Pins("io4", conn=ck_io, dir='o')),
            Subsignal("p4", Pins("io5", conn=ck_io, dir='o'))
            ),
        ])
    platform.build(IserdesTest(), do_program=False)

[bl0x]

I've found out, that cells_map.v has a few necessary inputs missing. I've made a PR #2367 to add the missing inputs (OCLK and OCLKB). The example above uses even more inputs, but they are not needed in this case.