feature(dcd_dwc2) : Added cache bypassing on esp32p4 while DMA is used

[roma-jam]

Requirements

ESP32P4 has Cache to access the RAM.
Cache is bypassing when:

1. DMA reads/writes the physical memory
2. CPU bypass Cache and directly reads/writes to the physical memory

When DMA is used for DCD DWC2 layer, it is necessary to synchronize data between memory and cache.
It could be achieved by two possible ways:

1. Explicitly synchronize the cache (implemented in feature(dcd_dwc2) : Added cache synchronization on esp32p4 while DMA is used #37)
2. Use direct access after DMA is done transferring (implemented here)

Description

All access to cache-related data were replaced with macroses, which return the regular (cache-able) address or noncache-able address based on the manually changed value (1) in the code.

Measurements

Measurements were done only to one example (tusb_msc), one buffer size and one chip.

ESP32P4

MSC Buffer size (bytes)	Slave Mode (R/W)	Buffer DMA direct-access (R/W)	Buffer DMA cache-able (R/W)
8192*	1.0 MB/s / 236.6 kB/s	1.0 MB/s / 236.6 kB/s	5.2 MB/s / 1.9 MB/s

Limitations

Currently, cache bypassing is only done for:

1. dcd_dwc2 itself
2. usbd_control layer
3. mscd class driver

But it should be done in every class, which allocates buffer/s statically to transfer data via DCD DWC2.

Breaking change

No breaking changes

Checklist

• Pull Request name has appropriate format (for example: "fix(dcd_dwc2): Resolved address selection when several phy are present")
• Optional: README.md updated
• CI passing

Related issues

No related issues