SOLVED: An ESP32(-S3) 3-cycle/tap fp32 FIR filter of arbitrary length and decimation (DSP-145)

[f4lc0n-asm]

Hello,

these 3-cycle/tap ASM FIR routines for ESP32(-S3) are drop-in replacements for the old 4-cycle/tap ones for ESP32. Just add preprocessor directives if needed. Turn off Task WDT before running the validation tests!
Benchmarks in the format: FIR_Length: new_ASM/old_ASM/C in cyc/tap (basically the number of cycles in a FIR loop for long FIRs):

 11: 6.05/6.47/17.10 |  21: 4.61/5.24/15.36 |   51: 3.66/4.50/14.26 |  101: 3.34/4.23/13.88
201: 3.17/4.12/13.69 | 501: 3.07/4.05/13.58 | 1001: 3.04/4.03/13.54 | 2001: 3.02/4.01/13.53

Cheers!

f4lc0n

FIR_fp32_3c_per_tap_v2.0.zip (7-Zip)
Added: decimating FIR with fixed input data length and with normal FIR coefficient order
Fixed: implemented C function prototype in the assembly
Fixed: C src code leftovers