diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 65a5fa29..790c2f82 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -40,6 +40,7 @@ jobs: - nanopi-r6c - nanopi-r6s - nanopc-t6 + - nanopc-cm3588-nas - blade3 - h88k CONFIGURATION: ${{ fromJSON(format('[{0}]', inputs.build-configs || '"Debug"')) }} diff --git a/README.md b/README.md index 7a555d46..c04db158 100644 --- a/README.md +++ b/README.md @@ -156,6 +156,7 @@ The paths above are relative to the root of the file system. That is, the `dtb` | `rk3588s-khadas-edge2` | Edge2 | | `rk3588-blade3-v101-linux` | Blade 3 | | `rk3588-nanopc-t6` | NanoPC T6 | +| `rk3588-nanopc-cm3588-nas` | NanoPC CM3588-NAS | | `rk3588s-nanopi-r6c` | NanoPi R6C | | `rk3588s-nanopi-r6s` | NanoPi R6S | | `rk3588-hinlink-h88k` | H88K | diff --git a/configs/nanopc-cm3588-nas.conf b/configs/nanopc-cm3588-nas.conf new file mode 100644 index 00000000..b5dc5b4b --- /dev/null +++ b/configs/nanopc-cm3588-nas.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.dsc +PLATFORM_NAME=NanoPC-CM3588-NAS +SOC=RK3588 diff --git a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-nanopc-cm3588-nas.dtb b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-nanopc-cm3588-nas.dtb new file mode 100755 index 00000000..44a11555 Binary files /dev/null and b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-nanopc-cm3588-nas.dtb differ diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/AcpiTables/AcpiTables.inf new file mode 100644 index 00000000..35d333b0 --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/AcpiTables/Dsdt.asl new file mode 100755 index 00000000..405ac5e3 --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/AcpiTables/Dsdt.asl @@ -0,0 +1,44 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + // include ("Gmac.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + // include ("Usb3Host2.asl") + } +} diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 00000000..3a4ffb69 --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,376 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + /* No GMAC here */ +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + break; + case 3: + break; + case 4: + GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3 + GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3 + break; + case 5: + GpioPinSetFunction(3, GPIO_PIN_PC7, 9); //i2c5_scl_m0 + GpioPinSetFunction(3, GPIO_PIN_PD0, 9); //i2c5_sda_m0 + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + break; + case 8: + GpioPinSetFunction(1, GPIO_PIN_PD6, 9); //i2c8_scl_m2 + GpioPinSetFunction(1, GPIO_PIN_PD7, 9); //i2c8_sda_m2 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + /* The "pinctrl/usb" section in the dts lists three _en pins for power. + They appear to correspond to the three usb ports on the NAS carrier board. */ + GpioPinWrite (1, GPIO_PIN_PA4, TRUE); + GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PB0, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); + GpioPinWrite (3, GPIO_PIN_PA5, TRUE); + GpioPinSetDirection (3, GPIO_PIN_PA5, GPIO_PIN_OUTPUT); + + /* Set GPIO1 PD2 (TYPEC5V_PWREN) output high to power the type-c port */ + GpioPinWrite (1, GPIO_PIN_PD2, TRUE); + GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT); + + // DEBUG((DEBUG_INFO, "Trying to enable on-board LED1\n")); + // GpioPinWrite (2, GPIO_PIN_PC0, TRUE); + // GpioPinSetDirection (2, GPIO_PIN_PC0, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE30X2: + GpioPinSetDirection (4, GPIO_PIN_PB3, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L0: // rtl8152b + GpioPinSetDirection (4, GPIO_PIN_PB4, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L1: // m.2 a+e key + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L2: //rtl8152b + GpioPinSetDirection (4, GPIO_PIN_PA4, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* output high to enable power */ + + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + break; + case PCIE_SEGMENT_PCIE20L0: + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + break; + default: + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + break; + case PCIE_SEGMENT_PCIE30X2: + GpioPinWrite (4, GPIO_PIN_PB3, !Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (4, GPIO_PIN_PB4, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinWrite (4, GPIO_PIN_PA2, !Enable); + break; + case PCIE_SEGMENT_PCIE20L2: + GpioPinWrite (4, GPIO_PIN_PA4, !Enable); + break; + default: + break; + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER0, + .ChannelID = PWM_CHANNEL1, + .PeriodNs = 4000000, + .DutyNs = 4000000, + .Polarity = FALSE, +}; // PWM0_CH1 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (1, GPIO_PIN_PD3, 0xB); // PWM1_M1 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (1, GPIO_PIN_PC6, FALSE); + GpioPinSetDirection (1, GPIO_PIN_PC6, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (1, GPIO_PIN_PC6, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + // GpioPinSetFunction(1, GPIO_PIN_PC4, 0); //jdet +} diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 00000000..b0ca9550 --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.Modules.fdf.inc b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.Modules.fdf.inc new file mode 100644 index 00000000..e1c7826d --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-nanopc-cm3588-nas.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.dsc b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.dsc new file mode 100644 index 00000000..3d7464fb --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.dsc @@ -0,0 +1,117 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Molly Sophia +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = NanoPC-CM3588-NAS + PLATFORM_VENDOR = FriendlyElec + PLATFORM_GUID = e5022309-24e1-46e0-9d40-dcbc7293e609 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"NanoPC CM3588-NAS" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"FriendlyElec" + gRockchipTokenSpaceGuid.PcdFamilyName|"NanoPi CM3588" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.friendlyelec.com/wiki/index.php/CM3588_NAS_Kit" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-nanopc-cm3588-nas" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # NanoPC CM3588 has one 2.5 GBE wired to the first PCIE2 port + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 } + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf