diff --git a/README.md b/README.md index 31b9752b..50eb4e41 100644 --- a/README.md +++ b/README.md @@ -6,6 +6,7 @@ This repository contains an UEFI firmware implementation based on EDK2 for vario - [Radxa ROCK 5A](https://radxa.com/products/rock5/5a/) - [Radxa ROCK 5 ITX](https://radxa.com/products/rock5/5itx/) - [Orange Pi 5](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html) +- [Orange Pi 5 Pro](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-Pro.html) - [Orange Pi 5 Plus](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-plus.html) - [ameriDroid Indiedroid Nova](https://indiedroid.us) - [Fydetab Duo](https://fydetabduo.com/) @@ -146,6 +147,7 @@ The paths above are relative to the root of the file system. That is, the `dtb` | `rk3588s-rock-5a` | ROCK 5A | | `rk3588-rock-5-itx` | ROCK 5 ITX | | `rk3588s-orangepi-5` | Orange Pi 5 | +| `rk3588s-orangepi-5-pro` | Orange Pi 5 Pro | | `rk3588-orangepi-5-plus` | Orange Pi 5 Plus | | `rk3588s-9tripod-linux` | Indiedroid Nova | | `rk3588s-fydetab-duo` | Fydetab Duo | @@ -306,7 +308,18 @@ The firmware can only be built on Linux currently. For Windows use WSL. For Ubuntu/Debian: ```bash - sudo apt install git gcc g++ build-essential gcc-aarch64-linux-gnu iasl python3-pyelftools uuid-dev + sudo apt install --yes \ + acpica-tools \ + build-essential \ + device-tree-compiler \ + g++ \ + gcc \ + gcc-aarch64-linux-gnu \ + git \ + python-is-python3 \ + python3 \ + python3-pyelftools \ + uuid-dev ``` For Arch Linux: ```bash diff --git a/configs/orangepi-5pro.conf b/configs/orangepi-5pro.conf new file mode 100644 index 00000000..344ed276 --- /dev/null +++ b/configs/orangepi-5pro.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/OrangePi/OrangePi5Pro/OrangePi5Pro.dsc +PLATFORM_NAME=OrangePi5Pro +SOC=RK3588 diff --git a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-orangepi-5-pro.dtb b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-orangepi-5-pro.dtb new file mode 100644 index 00000000..936eaa5b Binary files /dev/null and b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-orangepi-5-pro.dtb differ diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/AcpiTables/AcpiTables.inf new file mode 100644 index 00000000..306b9627 --- /dev/null +++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/AcpiTables/Dsdt.asl new file mode 100755 index 00000000..e3be7b47 --- /dev/null +++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/AcpiTables/Dsdt.asl @@ -0,0 +1,55 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S1_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C6" +#define BOARD_CODEC_I2C_ADDR 0x10 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD5 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + // include ("Gmac.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + + Scope (I2C6) { + include ("Es8388.asl") + } + } +} diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 00000000..2a3984e9 --- /dev/null +++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,332 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 850000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + /* This is not configured in the OrangePi5's Linux device tree + RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 1100000), */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + /* The OPi is officially configured for the 837500 voltage, but is still marked as avdd_0v75_s0 in the schematic and Linux device tree. rockchip says this voltage is set to improve HDMI stability. */ + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 837500), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux */ + /* Do not override, set by earlier boot stages. */ +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + /* Do not override, set by earlier boot stages. */ +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + + /* phy1 reset */ + GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 1: + /* phy1 reset */ + GpioPinWrite (3, GPIO_PIN_PB2, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + break; + case 4: + GpioPinSetFunction(3, GPIO_PIN_PA6, 9); //i2c4_scl_m0 + GpioPinSetFunction(3, GPIO_PIN_PA5, 9); //i2c4_sda_m0 + break; + case 5: + break; + case 6: + GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3 + GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3 + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + /* Set GPIO3 PC0 (TYPEC_EN) output high to power Type-C/USB2.0 ports */ + GpioPinWrite (3, GPIO_PIN_PC0, TRUE); + GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT); + + // DEBUG((DEBUG_INFO, "Trying to enable green led\n")); + // GpioPinWrite (1, GPIO_PIN_PA2, TRUE); + // GpioPinSetDirection (1, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset to gpio output mode */ + if(Segment == PCIE_SEGMENT_PCIE20L2) { // M.2 M Key + GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT); + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* nothing to power on */ +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + GpioPinWrite (3, GPIO_PIN_PD1, !Enable); + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER3, + .ChannelID = PWM_CHANNEL2, + .PeriodNs = 4000000, + .DutyNs = 4000000, + .Polarity = FALSE, +}; // PWM3_CH2 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (4, GPIO_PIN_PB2, 0xB); // PWM14_M1 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (1, GPIO_PIN_PA2, FALSE); + GpioPinSetDirection (1, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (1, GPIO_PIN_PA2, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + + GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet +} diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 00000000..0c146c79 --- /dev/null +++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/OrangePi5Pro.Modules.fdf.inc b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/OrangePi5Pro.Modules.fdf.inc new file mode 100644 index 00000000..8c0e5754 --- /dev/null +++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/OrangePi5Pro.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-orangepi-5-pro.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/OrangePi5Pro.dsc b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/OrangePi5Pro.dsc new file mode 100644 index 00000000..2ab23641 --- /dev/null +++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Pro/OrangePi5Pro.dsc @@ -0,0 +1,122 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Willzen Zou +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = OrangePi5Pro + PLATFORM_VENDOR = OrangePi + PLATFORM_GUID = 0f734438-7bb7-11ef-b25a-00163e21ee38 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588S-based platform + # +!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"Orange Pi 5 Pro" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Orange Pi" + gRockchipTokenSpaceGuid.PcdFamilyName|"Orange Pi 5" + gRockchipTokenSpaceGuid.PcdProductUrl|"http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-Pro.html" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-orangepi-5-pro" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x10 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x6 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42 + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S1Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf