|
9 | 9 | * any warranty of any kind, whether express or implied. |
10 | 10 | */ |
11 | 11 |
|
| 12 | +/dts-v1/; |
| 13 | + |
12 | 14 | / { |
13 | 15 | #address-cells = <2>; |
14 | 16 | #size-cells = <1>; |
15 | 17 | model = "amcc,bamboo"; |
16 | 18 | compatible = "amcc,bamboo"; |
17 | | - dcr-parent = <&/cpus/cpu@0>; |
| 19 | + dcr-parent = <&{/cpus/cpu@0}>; |
18 | 20 |
|
19 | 21 | aliases { |
20 | 22 | serial0 = &UART0; |
|
29 | 31 | device_type = "cpu"; |
30 | 32 | model = "PowerPC,440EP"; |
31 | 33 | reg = <0>; |
32 | | - clock-frequency = <1fca0550>; |
33 | | - timebase-frequency = <017d7840>; |
34 | | - i-cache-line-size = <20>; |
35 | | - d-cache-line-size = <20>; |
36 | | - i-cache-size = <8000>; |
37 | | - d-cache-size = <8000>; |
| 34 | + clock-frequency = <0x1fca0550>; |
| 35 | + timebase-frequency = <0x017d7840>; |
| 36 | + i-cache-line-size = <0x20>; |
| 37 | + d-cache-line-size = <0x20>; |
| 38 | + i-cache-size = <0x8000>; |
| 39 | + d-cache-size = <0x8000>; |
38 | 40 | dcr-controller; |
39 | 41 | dcr-access-method = "native"; |
40 | 42 | }; |
41 | 43 | }; |
42 | 44 |
|
43 | 45 | memory { |
44 | 46 | device_type = "memory"; |
45 | | - reg = <0 0 9000000>; |
| 47 | + reg = <0x0 0x0 0x9000000>; |
46 | 48 | }; |
47 | 49 |
|
48 | 50 | UIC0: interrupt-controller0 { |
49 | 51 | compatible = "ibm,uic-440ep","ibm,uic"; |
50 | 52 | interrupt-controller; |
51 | | - cell-index = <0>; |
52 | | - dcr-reg = <0c0 009>; |
53 | | - #address-cells = <0>; |
54 | | - #size-cells = <0>; |
55 | | - #interrupt-cells = <2>; |
56 | | - }; |
57 | | -/* |
58 | | - UIC1: interrupt-controller1 { |
59 | | - compatible = "ibm,uic-440ep","ibm,uic"; |
60 | | - interrupt-controller; |
61 | | - cell-index = <1>; |
62 | | - dcr-reg = <0d0 009>; |
63 | | - #address-cells = <0>; |
64 | | - #size-cells = <0>; |
65 | | - #interrupt-cells = <2>; |
66 | | - interrupts = <1e 4 1f 4>; |
67 | | - interrupt-parent = <&UIC0>; |
| 53 | + cell-index = <0x0>; |
| 54 | + dcr-reg = <0x0c0 0x009>; |
| 55 | + #address-cells = <0x0>; |
| 56 | + #size-cells = <0x0>; |
| 57 | + #interrupt-cells = <0x2>; |
68 | 58 | }; |
69 | | -*/ |
70 | 59 |
|
71 | 60 | SDR0: sdr { |
72 | 61 | compatible = "ibm,sdr-440ep"; |
73 | | - dcr-reg = <00e 002>; |
| 62 | + dcr-reg = <0x00e 0x002>; |
74 | 63 | }; |
75 | 64 |
|
76 | 65 | CPR0: cpr { |
77 | 66 | compatible = "ibm,cpr-440ep"; |
78 | | - dcr-reg = <00c 002>; |
| 67 | + dcr-reg = <0x00c 0x002>; |
79 | 68 | }; |
80 | 69 |
|
81 | 70 | plb { |
82 | 71 | compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4"; |
83 | 72 | #address-cells = <2>; |
84 | 73 | #size-cells = <1>; |
85 | 74 | ranges; |
86 | | - clock-frequency = <07f28154>; |
| 75 | + clock-frequency = <0x07f28154>; |
87 | 76 |
|
88 | 77 | SDRAM0: sdram { |
89 | 78 | compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; |
90 | | - dcr-reg = <010 2>; |
| 79 | + dcr-reg = <0x010 0x2>; |
91 | 80 | }; |
92 | 81 |
|
93 | 82 | DMA0: dma { |
94 | 83 | compatible = "ibm,dma-440ep", "ibm,dma-440gp"; |
95 | | - dcr-reg = <100 027>; |
| 84 | + dcr-reg = <0x100 0x027>; |
96 | 85 | }; |
97 | 86 |
|
98 | 87 | POB0: opb { |
|
102 | 91 | /* Bamboo is oddball in the 44x world and doesn't use the ERPN |
103 | 92 | * bits. |
104 | 93 | */ |
105 | | - ranges = <00000000 0 00000000 80000000 |
106 | | - 80000000 0 80000000 80000000>; |
| 94 | + ranges = <0x00000000 0x0 0x00000000 0x80000000 |
| 95 | + 0x80000000 0x0 0x80000000 0x80000000>; |
107 | 96 | /* interrupt-parent = <&UIC1>; */ |
108 | 97 | interrupts = <7 4>; |
109 | | - clock-frequency = <03f940aa>; |
| 98 | + clock-frequency = <0x03f940aa>; |
110 | 99 |
|
111 | 100 | EBC0: ebc { |
112 | 101 | compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; |
113 | | - dcr-reg = <012 2>; |
| 102 | + dcr-reg = <0x012 2>; |
114 | 103 | #address-cells = <2>; |
115 | 104 | #size-cells = <1>; |
116 | | - clock-frequency = <03f940aa>; |
| 105 | + clock-frequency = <0x03f940aa>; |
117 | 106 | interrupts = <5 1>; |
118 | 107 | /* interrupt-parent = <&UIC1>; */ |
119 | 108 | }; |
120 | 109 |
|
121 | 110 | UART0: serial@ef600300 { |
122 | 111 | device_type = "serial"; |
123 | 112 | compatible = "ns16550"; |
124 | | - reg = <ef600300 8>; |
125 | | - virtual-reg = <ef600300>; |
126 | | - clock-frequency = <00a8c000>; |
127 | | - current-speed = <1c200>; |
| 113 | + reg = <0xef600300 8>; |
| 114 | + virtual-reg = <0xef600300>; |
| 115 | + clock-frequency = <0x00a8c000>; |
| 116 | + current-speed = <0x1c200>; |
128 | 117 | interrupt-parent = <&UIC0>; |
129 | 118 | interrupts = <0 4>; |
130 | 119 | }; |
131 | 120 |
|
132 | 121 | UART1: serial@ef600400 { |
133 | 122 | device_type = "serial"; |
134 | 123 | compatible = "ns16550"; |
135 | | - reg = <ef600400 8>; |
136 | | - virtual-reg = <ef600400>; |
137 | | - clock-frequency = <00a8c000>; |
| 124 | + reg = <0xef600400 8>; |
| 125 | + virtual-reg = <0xef600400>; |
| 126 | + clock-frequency = <0x00a8c000>; |
138 | 127 | current-speed = <0>; |
139 | 128 | interrupt-parent = <&UIC0>; |
140 | 129 | interrupts = <1 4>; |
141 | 130 | }; |
142 | | -/* |
143 | | - UART2: serial@ef600500 { |
144 | | - device_type = "serial"; |
145 | | - compatible = "ns16550"; |
146 | | - reg = <ef600500 8>; |
147 | | - virtual-reg = <ef600500>; |
148 | | - clock-frequency = <0>; |
149 | | - current-speed = <0>; |
150 | | - interrupt-parent = <&UIC0>; |
151 | | - interrupts = <3 4>; |
152 | | - }; |
153 | | - |
154 | | - UART3: serial@ef600600 { |
155 | | - device_type = "serial"; |
156 | | - compatible = "ns16550"; |
157 | | - reg = <ef600600 8>; |
158 | | - virtual-reg = <ef600600>; |
159 | | - clock-frequency = <0>; |
160 | | - current-speed = <0>; |
161 | | - interrupt-parent = <&UIC0>; |
162 | | - interrupts = <4 4>; |
163 | | - }; |
164 | 131 |
|
165 | | -*/ |
166 | 132 | IIC0: i2c@ef600700 { |
167 | 133 | device_type = "i2c"; |
168 | 134 | compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; |
169 | | - reg = <ef600700 14>; |
| 135 | + reg = <0xef600700 0x14>; |
170 | 136 | interrupt-parent = <&UIC0>; |
171 | 137 | interrupts = <2 4>; |
172 | 138 | }; |
173 | 139 |
|
174 | 140 | IIC1: i2c@ef600800 { |
175 | 141 | device_type = "i2c"; |
176 | 142 | compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; |
177 | | - reg = <ef600800 14>; |
| 143 | + reg = <0xef600800 14>; |
178 | 144 | interrupt-parent = <&UIC0>; |
179 | 145 | interrupts = <7 4>; |
180 | 146 | }; |
181 | 147 |
|
182 | 148 | ZMII0: emac-zmii@ef600d00 { |
183 | 149 | device_type = "zmii-interface"; |
184 | 150 | compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; |
185 | | - reg = <ef600d00 c>; |
| 151 | + reg = <0xef600d00 0xc>; |
186 | 152 | }; |
187 | 153 |
|
188 | 154 | }; |
|
194 | 160 | #address-cells = <3>; |
195 | 161 | compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; |
196 | 162 | primary; |
197 | | - reg = <0 eec00000 8 /* Config space access */ |
198 | | - 0 eed00000 4 /* IACK */ |
199 | | - 0 eed00000 4 /* Special cycle */ |
200 | | - 0 ef400000 40>; /* Internal registers */ |
| 163 | + reg = <0 0xeec00000 8 /* Config space access */ |
| 164 | + 0 0xeed00000 4 /* IACK */ |
| 165 | + 0 0xeed00000 4 /* Special cycle */ |
| 166 | + 0 0xef400000 0x40>; /* Internal registers */ |
201 | 167 |
|
202 | 168 | /* Outbound ranges, one memory and one IO, |
203 | 169 | * later cannot be changed. Chip supports a second |
204 | 170 | * IO range but we don't use it for now |
205 | 171 | */ |
206 | | - ranges = <02000000 0 a0000000 0 a0000000 0 20000000 |
207 | | - 01000000 0 00000000 0 e8000000 0 00010000>; |
| 172 | + ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000 |
| 173 | + 0x01000000 0 0x00000000 0 0xe8000000 0 0x00010000>; |
208 | 174 |
|
209 | 175 | /* Inbound 2GB range starting at 0 */ |
210 | | - dma-ranges = <42000000 0 0 0 0 0 80000000>; |
| 176 | + dma-ranges = <0x42000000 0 0 0 0 0 0x80000000>; |
211 | 177 |
|
212 | 178 | /* Bamboo has all 4 IRQ pins tied together per slot */ |
213 | | - interrupt-map-mask = <f800 0 0 0>; |
| 179 | + interrupt-map-mask = <0xf800 0 0 0>; |
214 | 180 | interrupt-map = < |
215 | 181 | /* IDSEL 1 */ |
216 | | - 0800 0 0 0 &UIC0 1c 8 |
| 182 | + 0x0800 0 0 0 &UIC0 0x1c 8 |
217 | 183 |
|
218 | 184 | /* IDSEL 2 */ |
219 | | - 1000 0 0 0 &UIC0 1b 8 |
| 185 | + 0x1000 0 0 0 &UIC0 0x1b 8 |
220 | 186 |
|
221 | 187 | /* IDSEL 3 */ |
222 | | - 1800 0 0 0 &UIC0 1a 8 |
| 188 | + 0x1800 0 0 0 &UIC0 0x1a 8 |
223 | 189 |
|
224 | 190 | /* IDSEL 4 */ |
225 | | - 2000 0 0 0 &UIC0 19 8 |
| 191 | + 0x2000 0 0 0 &UIC0 0x19 8 |
226 | 192 | >; |
227 | 193 | }; |
228 | 194 |
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