This is list of all MIPS1 instructions and their implementation status in QtMips.
Explanation of checkboxes:
- Not tested
- Tested
- ADD
- ADDI
- ADDIU
- ADDU
- CLO
- CLZ
- DIV
- DIVU
- MADD
- MADDU
- MSUB
- MSUBU
- MUL
- MULT
- MULTU
- SLT
- SLTI
- SLTIU
- SLTU
- SUB
- SUBU
- B
- BAL
- BEQ
- BGEZ
- BGEZAL
- BGTZ
- BLEZ
- BLTZ
- BLTZAL
- BNE
- J
- JAL
- JALR
- JR
- NOP
- SSNOP
- LB
- LBU
- LH
- LHU
- LL
- LW
- LWL
- LWR
- PREF
- SB
- SC
- SD
- SH
- SW
- SWL
- SWR
- SYNC
- AND
- ANDI
- LUI
- NOR
- OR
- ORI
- XOR
- XORI
- MFHI
- MFLO
- MTHI
- MTHO
- MOVN
- MOVZ
- MOVF, MOVT won't be implemented as floating coprocessor won't be implemented
- SLL
- SLLV
- SRA
- SRAV
- SRL
- SRLV
Following instruction will be implemented but only as dummy ones as we are not implementing privileged instructions. They will all result to exception and core execution stop.
- BREAK
- TEQ
- TEQI
- TGE
- TGEI
- TGEIU
- TGEU
- TLT
- TLTI
- TLTIU
- TLTU
- TNE
- TNEI
- SYSCALL won't be implemented at all
None of these instructions will be implemented as they are marked as obsolete and they shouldn't be used by compiler and the same way by programmers.
No FPU instruction will be implemented as no FPU is planned to be implemented.
None of these will be implemented as coprocessor 2 won't be implemented.
None of these will be implemented as privileged state won't be implemented.
No instruction will be implemented as no ejtag support.