diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala
index 997abc2e52d..e9b00689aa9 100644
--- a/src/main/scala/groundtest/Configs.scala
+++ b/src/main/scala/groundtest/Configs.scala
@@ -10,7 +10,6 @@ import freechips.rocketchip.devices.debug.{DebugModuleKey}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.BaseConfig
 import freechips.rocketchip.rocket.{DCacheParams}
-import freechips.rocketchip.tile.{XLen}
 
 /** Actual testing target Configs */
 
@@ -39,7 +38,8 @@ class WithTraceGen(
   n: Int = 2,
   overrideMemOffset: Option[BigInt] = None)(
   params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
-  nReqs: Int = 8192
+  nReqs: Int = 8192,
+  wordBits: Int = 32
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
     val prev = up(TilesLocated(InSubsystem), site)
@@ -50,7 +50,7 @@ class WithTraceGen(
         tileParams = TraceGenParams(
           tileId = i + idOffset,
           dcache = Some(dcp),
-          wordBits = site(XLen),
+          wordBits = wordBits,
           addrBits = 32,
           addrBag = {
             val nSets = dcp.nSets
diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala
index dfcb6cc426b..588f930978d 100644
--- a/src/main/scala/groundtest/TraceGen.scala
+++ b/src/main/scala/groundtest/TraceGen.scala
@@ -62,11 +62,11 @@ import freechips.rocketchip.prci.{ClockSinkParameters, ClockCrossingType}
 //     to repeatedly recompile with a different address bag.)
 
 case class TraceGenParams(
-    wordBits: Int, // p(XLen) 
-    addrBits: Int, // p(PAddrBits)
-    addrBag: List[BigInt], // p(AddressBag)
+    wordBits: Int,
+    addrBits: Int,
+    addrBag: List[BigInt],
     maxRequests: Int,
-    memStart: BigInt, //p(ExtMem).base
+    memStart: BigInt,
     numGens: Int,
     dcache: Option[DCacheParams] = Some(DCacheParams()),
     tileId: Int = 0
diff --git a/src/main/scala/rocket/Configs.scala b/src/main/scala/rocket/Configs.scala
new file mode 100644
index 00000000000..1e2cc94c655
--- /dev/null
+++ b/src/main/scala/rocket/Configs.scala
@@ -0,0 +1,283 @@
+package freechips.rocketchip.rocket
+
+import chisel3.util._
+
+import org.chipsalliance.cde.config._
+import org.chipsalliance.diplomacy.lazymodule._
+
+import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType}
+import freechips.rocketchip.subsystem.{TilesLocated, NumTiles, HierarchicalLocation, RocketCrossingParams, SystemBusKey, CacheBlockBytes, RocketTileAttachParams, InSubsystem, InCluster, HierarchicalElementMasterPortParams, HierarchicalElementSlavePortParams, CBUS, CCBUS, ClustersLocated, TileAttachConfig, CloneTileAttachParams}
+import freechips.rocketchip.tile.{RocketTileParams, RocketTileBoundaryBufferParams}
+import scala.reflect.ClassTag
+
+
+class WithNBigCores(
+  n: Int,
+  location: HierarchicalLocation,
+  crossing: RocketCrossingParams,
+) extends Config((site, here, up) => {
+  case TilesLocated(`location`) => {
+    val prev = up(TilesLocated(`location`), site)
+    val idOffset = up(NumTiles)
+    val big = RocketTileParams(
+      core   = RocketCoreParams(mulDiv = Some(MulDivParams(
+        mulUnroll = 8,
+        mulEarlyOut = true,
+        divEarlyOut = true))),
+      dcache = Some(DCacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nMSHRs = 0,
+        blockBytes = site(CacheBlockBytes))),
+      icache = Some(ICacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        blockBytes = site(CacheBlockBytes))))
+    List.tabulate(n)(i => RocketTileAttachParams(
+      big.copy(tileId = i + idOffset),
+      crossing
+    )) ++ prev
+  }
+  case NumTiles => up(NumTiles) + n
+}) {
+  def this(n: Int, location: HierarchicalLocation = InSubsystem) = this(n, location, RocketCrossingParams(
+    master = HierarchicalElementMasterPortParams.locationDefault(location),
+    slave = HierarchicalElementSlavePortParams.locationDefault(location),
+    mmioBaseAddressPrefixWhere = location match {
+      case InSubsystem => CBUS
+      case InCluster(clusterId) => CCBUS(clusterId)
+    }
+  ))
+}
+
+class WithNMedCores(
+  n: Int,
+  crossing: RocketCrossingParams = RocketCrossingParams(),
+) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => {
+    val prev = up(TilesLocated(InSubsystem), site)
+    val idOffset = up(NumTiles)
+    val med = RocketTileParams(
+      core = RocketCoreParams(fpu = None),
+      btb = None,
+      dcache = Some(DCacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBSets = 1,
+        nTLBWays = 4,
+        nMSHRs = 0,
+        blockBytes = site(CacheBlockBytes))),
+      icache = Some(ICacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBSets = 1,
+        nTLBWays = 4,
+        blockBytes = site(CacheBlockBytes))))
+    List.tabulate(n)(i => RocketTileAttachParams(
+      med.copy(tileId = i + idOffset),
+      crossing
+    )) ++ prev
+  }
+  case NumTiles => up(NumTiles) + n
+})
+
+class WithNSmallCores(
+  n: Int,
+  crossing: RocketCrossingParams = RocketCrossingParams()
+) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => {
+    val prev = up(TilesLocated(InSubsystem), site)
+    val idOffset = up(NumTiles)
+    val small = RocketTileParams(
+      core = RocketCoreParams(useVM = false, fpu = None),
+      btb = None,
+      dcache = Some(DCacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBSets = 1,
+        nTLBWays = 4,
+        nMSHRs = 0,
+        blockBytes = site(CacheBlockBytes))),
+      icache = Some(ICacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBSets = 1,
+        nTLBWays = 4,
+        blockBytes = site(CacheBlockBytes))))
+    List.tabulate(n)(i => RocketTileAttachParams(
+      small.copy(tileId = i + idOffset),
+      crossing
+    )) ++ prev
+  }
+  case NumTiles => up(NumTiles) + n
+})
+
+class With1TinyCore extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => {
+    val tiny = RocketTileParams(
+      core = RocketCoreParams(
+        xLen = 32,
+        pgLevels = 2, // sv32
+        useVM = false,
+        fpu = None,
+        mulDiv = Some(MulDivParams(mulUnroll = 8))),
+      btb = None,
+      dcache = Some(DCacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 256, // 16Kb scratchpad
+        nWays = 1,
+        nTLBSets = 1,
+        nTLBWays = 4,
+        nMSHRs = 0,
+        blockBytes = site(CacheBlockBytes),
+        scratch = Some(0x80000000L))),
+      icache = Some(ICacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBSets = 1,
+        nTLBWays = 4,
+        blockBytes = site(CacheBlockBytes)))
+    )
+    List(RocketTileAttachParams(
+      tiny,
+      RocketCrossingParams(
+        crossingType = SynchronousCrossing(),
+        master = HierarchicalElementMasterPortParams())
+    ))
+  }
+  case NumTiles => 1
+  case ClustersLocated(_) => Nil
+})
+
+class RocketTileAttachConfig(f: RocketTileAttachParams => RocketTileAttachParams) extends TileAttachConfig[RocketTileAttachParams](f)
+
+class RocketTileConfig(f: RocketTileParams => RocketTileParams) extends RocketTileAttachConfig(tp => tp.copy(
+  tileParams = f(tp.tileParams)
+))
+
+class RocketCrossingConfig(f: RocketCrossingParams => RocketCrossingParams) extends RocketTileAttachConfig(tp => tp.copy(
+  crossingParams = f(tp.crossingParams)
+))
+
+class RocketCoreConfig(f: RocketCoreParams => RocketCoreParams) extends RocketTileConfig(tp => tp.copy(
+  core = f(tp.core)
+))
+
+class RocketICacheConfig(f: ICacheParams => ICacheParams) extends RocketTileConfig(tp => tp.copy(
+  icache = tp.icache.map(ic => f(ic))
+))
+
+class RocketDCacheConfig(f: DCacheParams => DCacheParams) extends RocketTileConfig(tp => tp.copy(
+  dcache = tp.dcache.map(dc => f(dc))
+))
+
+class WithL1ICacheSets(sets: Int)                      extends RocketICacheConfig(_.copy(nSets=sets))
+class WithL1ICacheWays(ways: Int)                      extends RocketICacheConfig(_.copy(nWays=ways))
+class WithL1ICacheECC(dataECC: String, tagECC: String) extends RocketICacheConfig(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC)))
+class WithL1ICacheRowBits(n: Int)                      extends RocketICacheConfig(_.copy(rowBits = n))
+class WithL1ICacheTLBSets(sets: Int)                   extends RocketICacheConfig(_.copy(nTLBSets = sets))
+class WithL1ICacheTLBWays(ways: Int)                   extends RocketICacheConfig(_.copy(nTLBWays = ways))
+class WithL1ICacheTLBBasePageSectors(sectors: Int)     extends RocketICacheConfig(_.copy(nTLBBasePageSectors = sectors))
+class WithL1ICacheTLBSuperpages(superpages: Int)       extends RocketICacheConfig(_.copy(nTLBSuperpages = superpages))
+class WithL1ICacheBlockBytes(bytes: Int = 64)          extends RocketICacheConfig(_.copy(blockBytes = bytes))
+
+class WithL1DCacheSets(sets: Int)                      extends RocketDCacheConfig(_.copy(nSets=sets))
+class WithL1DCacheWays(ways: Int)                      extends RocketDCacheConfig(_.copy(nWays=ways))
+class WithL1DCacheECC(dataECC: String, tagECC: String) extends RocketDCacheConfig(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC)))
+class WithL1DCacheRowBits(n: Int)                      extends RocketDCacheConfig(_.copy(rowBits = n))
+class WithL1DCacheTLBSets(sets: Int)                   extends RocketDCacheConfig(_.copy(nTLBSets = sets))
+class WithL1DCacheTLBWays(ways: Int)                   extends RocketDCacheConfig(_.copy(nTLBWays = ways))
+class WithL1DCacheTLBBasePageSectors(sectors: Int)     extends RocketDCacheConfig(_.copy(nTLBBasePageSectors = sectors))
+class WithL1DCacheTLBSuperpages(superpages: Int)       extends RocketDCacheConfig(_.copy(nTLBSuperpages = superpages))
+class WithL1DCacheBlockBytes(bytes: Int = 64)          extends RocketDCacheConfig(_.copy(blockBytes = bytes))
+class WithL1DCacheNonblocking(nMSHRs: Int)             extends RocketDCacheConfig(_.copy(nMSHRs = nMSHRs))
+class WithL1DCacheClockGating                          extends RocketDCacheConfig(_.copy(clockGate = true))
+class WithL1DCacheDTIMAddress(address: BigInt)         extends RocketDCacheConfig(_.copy(scratch = Some(address)))
+
+class WithScratchpadsOnly extends RocketTileConfig(tp => tp.copy(
+  core = tp.core.copy(useVM = false),
+  dcache = tp.dcache.map(_.copy(
+    nSets = 256, // 16Kb scratchpad
+    nWays = 1,
+    scratch = Some(0x80000000L)))
+))
+
+class WithCacheRowBits(n: Int) extends RocketTileConfig(tp => tp.copy(
+  dcache = tp.dcache.map(_.copy(rowBits = n)),
+  icache = tp.icache.map(_.copy(rowBits = n))
+))
+
+class WithBEU(addr: BigInt) extends RocketTileConfig(_.copy(beuAddr = Some(addr)))
+class WithBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends RocketTileConfig(_.copy(boundaryBuffers = buffers))
+
+class WithRV32 extends RocketCoreConfig(c => c.copy(
+  xLen = 32,
+  pgLevels = 2, // sv32
+  fpu = c.fpu.map(_.copy(fLen = 32)),
+  mulDiv = Some(MulDivParams(mulUnroll = 8))
+))
+
+class WithoutVM                                           extends RocketCoreConfig(_.copy(useVM = false))
+class WithCFlushEnabled                                   extends RocketCoreConfig(_.copy(haveCFlush = true))
+class WithNBreakpoints(hwbp: Int)                         extends RocketCoreConfig(_.copy(nBreakpoints = hwbp))
+class WithHypervisor(hext: Boolean = true)                extends RocketCoreConfig(_.copy(useHypervisor = hext))
+class WithCease(enable: Boolean = true)                   extends RocketCoreConfig(_.copy(haveCease = enable))
+class WithCoreClockGatingEnabled                          extends RocketCoreConfig(_.copy(clockGate = true))
+class WithPgLevels(n: Int)                                extends RocketCoreConfig(_.copy(pgLevels = n))
+class WithSV48                                            extends WithPgLevels(4)
+class WithSV39                                            extends WithPgLevels(3)
+
+// Simulation-only configs
+class WithNoSimulationTimeout extends RocketCoreConfig(_.copy(haveSimTimeout = false))
+class WithDebugROB(enable: Boolean = true, size: Int = 0) extends RocketCoreConfig(_.copy(debugROB = Option.when(enable)(DebugROBParams(size))))
+
+// FPU configs
+class WithoutFPU            extends RocketCoreConfig(_.copy(fpu = None))
+class WithFP16              extends RocketCoreConfig(c => c.copy(fpu = c.fpu.map(_.copy(minFLen = 16))))
+class WithFPUWithoutDivSqrt extends RocketCoreConfig(c => c.copy(fpu = c.fpu.map(_.copy(divSqrt = false))))
+
+// mul-div configs
+class WithFastMulDiv extends RocketCoreConfig(c => c.copy(mulDiv = Some(
+  MulDivParams(mulUnroll = 8, mulEarlyOut = c.xLen > 32, divEarlyOut = true)
+)))
+class WithCustomFastMulDiv(mUnroll: Int = 8, mEarlyOut: Boolean = true, dUnroll: Int = 1, dEarlyOut: Boolean = true, dEarlyOutGranularity: Int = 1) extends RocketCoreConfig(_.copy(mulDiv = Some(
+  MulDivParams(mulUnroll = mUnroll, mulEarlyOut = mEarlyOut, divUnroll = dUnroll, divEarlyOut = dEarlyOut, divEarlyOutGranularity = dEarlyOutGranularity)
+)))
+class WithoutMulDiv extends RocketCoreConfig(_.copy(mulDiv = None))
+
+// Branch-prediction configs
+class WithDefaultBtb extends RocketTileConfig(t => t.copy(btb = Some(BTBParams())))
+class WithNoBtb      extends RocketTileConfig(_.copy(btb = None))
+
+// Tile CDC configs
+class WithCDC(crossingType: ClockCrossingType = SynchronousCrossing()) extends RocketCrossingConfig(_.copy(crossingType = crossingType))
+class WithSeperateClockReset                                           extends RocketCrossingConfig(_.copy(forceSeparateClockReset = true))
+class WithSynchronousCDCs                                              extends WithCDC(SynchronousCrossing())
+class WithAsynchronousCDCs(depth: Int, sync: Int)                      extends WithCDC(AsynchronousCrossing(depth, sync))
+class WithRationalCDCs                                                 extends WithCDC(RationalCrossing())
+
+
+
+class WithCloneRocketTiles(
+  n: Int = 1,
+  cloneTileId: Int = 0,
+  location: HierarchicalLocation = InSubsystem,
+  cloneLocation: HierarchicalLocation = InSubsystem
+) extends Config((site, here, up) => {
+  case TilesLocated(`location`) => {
+    val prev = up(TilesLocated(location), site)
+    val idOffset = up(NumTiles)
+    val tileAttachParams = up(TilesLocated(cloneLocation)).find(_.tileParams.tileId == cloneTileId)
+      .get.asInstanceOf[RocketTileAttachParams]
+    (0 until n).map { i =>
+      CloneTileAttachParams(cloneTileId, tileAttachParams.copy(
+        tileParams = tileAttachParams.tileParams.copy(tileId = i + idOffset)
+      ))
+    } ++ prev
+  }
+  case NumTiles => up(NumTiles) + n
+})
+
diff --git a/src/main/scala/rocket/RVC.scala b/src/main/scala/rocket/RVC.scala
index 71ac35ee480..c9252c086cf 100644
--- a/src/main/scala/rocket/RVC.scala
+++ b/src/main/scala/rocket/RVC.scala
@@ -197,12 +197,12 @@ class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) ext
 
   if (usingCompressed) {
     io.rvc := io.in(1,0) =/= 3.U
-    val decoder = new RVCDecoder(io.in, p(XLen), fLen, useAddiForMv)
+    val decoder = new RVCDecoder(io.in, xLen, fLen, useAddiForMv)
     io.out := decoder.decode
     io.ill := decoder.ill
   } else {
     io.rvc := false.B
-    io.out := new RVCDecoder(io.in, p(XLen), fLen, useAddiForMv).passthrough
+    io.out := new RVCDecoder(io.in, xLen, fLen, useAddiForMv).passthrough
     io.ill := false.B // only used for RVC
   }
 }
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
index 8fbe232824e..605a5fd12b3 100644
--- a/src/main/scala/rocket/RocketCore.scala
+++ b/src/main/scala/rocket/RocketCore.scala
@@ -13,6 +13,8 @@ import freechips.rocketchip.util.property
 import scala.collection.mutable.ArrayBuffer
 
 case class RocketCoreParams(
+  xLen: Int = 64,
+  pgLevels: Int = 3, // sv39 default
   bootFreqHz: BigInt = 0,
   useVM: Boolean = true,
   useUser: Boolean = false,
diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala
index e0a6ddea797..8cc4a2c67c9 100644
--- a/src/main/scala/rocket/TLB.scala
+++ b/src/main/scala/rocket/TLB.scala
@@ -23,7 +23,6 @@ import freechips.rocketchip.util.UIntIsOneOf
 import freechips.rocketchip.util.SeqToAugmentedSeq
 import freechips.rocketchip.util.SeqBoolBitwiseOps
 
-case object PgLevels extends Field[Int](2)
 case object ASIdBits extends Field[Int](0)
 case object VMIdBits extends Field[Int](0)
 
diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
index 195fff022ef..37001b39fd3 100644
--- a/src/main/scala/subsystem/Configs.scala
+++ b/src/main/scala/subsystem/Configs.scala
@@ -19,42 +19,44 @@ import freechips.rocketchip.diplomacy.{
 import freechips.rocketchip.resources.{
   DTSModel, DTSCompat, DTSTimebase, BigIntHexContext
 }
-import freechips.rocketchip.rocket.{PgLevels, RocketCoreParams, MulDivParams, DCacheParams, ICacheParams, BTBParams, DebugROBParams}
 import freechips.rocketchip.tile.{
-  XLen, MaxHartIdBits, RocketTileParams, BuildRoCC, AccumulatorExample, OpcodeSet, TranslatorExample, CharacterCountExample, BlackBoxExample
+  MaxHartIdBits, RocketTileParams, BuildRoCC, AccumulatorExample, OpcodeSet, TranslatorExample, CharacterCountExample, BlackBoxExample
 }
 import freechips.rocketchip.util.ClockGateModelFile
+import scala.reflect.ClassTag
+
+case object MaxXLen extends Field[Int]
 
 class BaseSubsystemConfig extends Config ((site, here, up) => {
   // Tile parameters
-  case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
-  case XLen => 64 // Applies to all cores
+  case MaxXLen => (site(PossibleTileLocations).flatMap(loc => site(TilesLocated(loc)))
+    .map(_.tileParams.core.xLen) :+ 32).max
   case MaxHartIdBits => log2Up((site(PossibleTileLocations).flatMap(loc => site(TilesLocated(loc)))
       .map(_.tileParams.tileId) :+ 0).max+1)
   // Interconnect parameters
   case SystemBusKey => SystemBusParams(
-    beatBytes = site(XLen)/8,
+    beatBytes = 8,
     blockBytes = site(CacheBlockBytes))
   case ControlBusKey => PeripheryBusParams(
-    beatBytes = site(XLen)/8,
+    beatBytes = 8,
     blockBytes = site(CacheBlockBytes),
     dtsFrequency = Some(100000000), // Default to 100 MHz cbus clock
     errorDevice = Some(BuiltInErrorDeviceParams(
-      errorParams = DevNullParams(List(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=4096))))
+      errorParams = DevNullParams(List(AddressSet(0x3000, 0xfff)), maxAtomic=8, maxTransfer=4096))))
   case PeripheryBusKey => PeripheryBusParams(
-    beatBytes = site(XLen)/8,
+    beatBytes = 8,
     blockBytes = site(CacheBlockBytes),
     dtsFrequency = Some(100000000)) // Default to 100 MHz pbus clock
   case MemoryBusKey => MemoryBusParams(
-    beatBytes = site(XLen)/8,
+    beatBytes = 8,
     blockBytes = site(CacheBlockBytes))
   case FrontBusKey => FrontBusParams(
-    beatBytes = site(XLen)/8,
+    beatBytes = 8,
     blockBytes = site(CacheBlockBytes))
   // Additional device Parameters
   case BootROMLocated(InSubsystem) => Some(BootROMParams(contentFileName = "./bootrom/bootrom.img"))
   case HasTilesExternalResetVectorKey => false
-  case DebugModuleKey => Some(DefaultDebugModuleParams(site(XLen)))
+  case DebugModuleKey => Some(DefaultDebugModuleParams(64))
   case CLINTKey => Some(CLINTParams())
   case PLICKey => Some(PLICParams())
   case TilesLocated(InSubsystem) => Nil
@@ -102,148 +104,6 @@ class WithCoherentBusTopology extends Config((site, here, up) => {
       driveMBusClockFromSBus = site(DriveClocksFromSBus)))
 })
 
-class WithNBigCores(
-  n: Int,
-  location: HierarchicalLocation,
-  crossing: RocketCrossingParams,
-) extends Config((site, here, up) => {
-  case TilesLocated(`location`) => {
-    val prev = up(TilesLocated(`location`), site)
-    val idOffset = up(NumTiles)
-    val big = RocketTileParams(
-      core   = RocketCoreParams(mulDiv = Some(MulDivParams(
-        mulUnroll = 8,
-        mulEarlyOut = true,
-        divEarlyOut = true))),
-      dcache = Some(DCacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nMSHRs = 0,
-        blockBytes = site(CacheBlockBytes))),
-      icache = Some(ICacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        blockBytes = site(CacheBlockBytes))))
-    List.tabulate(n)(i => RocketTileAttachParams(
-      big.copy(tileId = i + idOffset),
-      crossing
-    )) ++ prev
-  }
-  case NumTiles => up(NumTiles) + n
-}) {
-  def this(n: Int, location: HierarchicalLocation = InSubsystem) = this(n, location, RocketCrossingParams(
-    master = HierarchicalElementMasterPortParams.locationDefault(location),
-    slave = HierarchicalElementSlavePortParams.locationDefault(location),
-    mmioBaseAddressPrefixWhere = location match {
-      case InSubsystem => CBUS
-      case InCluster(clusterId) => CCBUS(clusterId)
-    }
-  ))
-}
-
-
-
-class WithNMedCores(
-  n: Int,
-  crossing: RocketCrossingParams = RocketCrossingParams(),
-) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => {
-    val prev = up(TilesLocated(InSubsystem), site)
-    val idOffset = up(NumTiles)
-    val med = RocketTileParams(
-      core = RocketCoreParams(fpu = None),
-      btb = None,
-      dcache = Some(DCacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nSets = 64,
-        nWays = 1,
-        nTLBSets = 1,
-        nTLBWays = 4,
-        nMSHRs = 0,
-        blockBytes = site(CacheBlockBytes))),
-      icache = Some(ICacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nSets = 64,
-        nWays = 1,
-        nTLBSets = 1,
-        nTLBWays = 4,
-        blockBytes = site(CacheBlockBytes))))
-    List.tabulate(n)(i => RocketTileAttachParams(
-      med.copy(tileId = i + idOffset),
-      crossing
-    )) ++ prev
-  }
-  case NumTiles => up(NumTiles) + n
-})
-
-class WithNSmallCores(
-  n: Int,
-  crossing: RocketCrossingParams = RocketCrossingParams()
-) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => {
-    val prev = up(TilesLocated(InSubsystem), site)
-    val idOffset = up(NumTiles)
-    val small = RocketTileParams(
-      core = RocketCoreParams(useVM = false, fpu = None),
-      btb = None,
-      dcache = Some(DCacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nSets = 64,
-        nWays = 1,
-        nTLBSets = 1,
-        nTLBWays = 4,
-        nMSHRs = 0,
-        blockBytes = site(CacheBlockBytes))),
-      icache = Some(ICacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nSets = 64,
-        nWays = 1,
-        nTLBSets = 1,
-        nTLBWays = 4,
-        blockBytes = site(CacheBlockBytes))))
-    List.tabulate(n)(i => RocketTileAttachParams(
-      small.copy(tileId = i + idOffset),
-      crossing
-    )) ++ prev
-  }
-  case NumTiles => up(NumTiles) + n
-})
-
-class With1TinyCore extends Config((site, here, up) => {
-  case XLen => 32
-  case TilesLocated(InSubsystem) => {
-    val tiny = RocketTileParams(
-      core = RocketCoreParams(
-        useVM = false,
-        fpu = None,
-        mulDiv = Some(MulDivParams(mulUnroll = 8))),
-      btb = None,
-      dcache = Some(DCacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nSets = 256, // 16Kb scratchpad
-        nWays = 1,
-        nTLBSets = 1,
-        nTLBWays = 4,
-        nMSHRs = 0,
-        blockBytes = site(CacheBlockBytes),
-        scratch = Some(0x80000000L))),
-      icache = Some(ICacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nSets = 64,
-        nWays = 1,
-        nTLBSets = 1,
-        nTLBWays = 4,
-        blockBytes = site(CacheBlockBytes)))
-    )
-    List(RocketTileAttachParams(
-      tiny,
-      RocketCrossingParams(
-        crossingType = SynchronousCrossing(),
-        master = HierarchicalElementMasterPortParams())
-    ))
-  }
-  case NumTiles => 1
-  case ClustersLocated(_) => Nil
-})
-
 class WithCluster(
   clusterId: Int,
   location: HierarchicalLocation = InSubsystem,
@@ -275,177 +135,6 @@ class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => {
   case BroadcastKey => up(BroadcastKey, site).copy(nTrackers = n)
 })
 
-// This is the number of icache sets for all Rocket tiles
-class WithL1ICacheSets(sets: Int) extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      icache = tp.tileParams.icache.map(_.copy(nSets = sets))))
-    case t => t
-  }
-})
-
-// This is the number of icache sets for all Rocket tiles
-class WithL1DCacheSets(sets: Int) extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(nSets = sets))))
-    case t => t
-  }
-})
-
-class WithL1ICacheWays(ways: Int) extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      icache = tp.tileParams.icache.map(_.copy(nWays = ways))))
-    case t => t
-  }
-})
-
-class WithL1DCacheWays(ways: Int) extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(nWays = ways))))
-    case t => t
-  }
-})
-
-class WithL1ICacheECC(dataECC: String, tagECC: String) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      icache = tp.tileParams.icache.map(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC)))))
-    case t => t
-  }
-})
-
-class WithL1DCacheECC(dataECC: String, tagECC: String) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(dataECC = Some(dataECC), tagECC = Some(tagECC), dataECCBytes=8))))
-    case t => t
-  }
-})
-
-class WithL1ICacheTLBSets(tlbsets: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      icache = tp.tileParams.icache.map(_.copy(nTLBSets = tlbsets))))
-    case t => t
-  }
-})
-
-class WithL1DCacheTLBSets(tlbsets: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(nTLBSets = tlbsets))))
-    case t => t
-  }
-})
-
-class WithL1ICacheTLBWays(tlbways: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      icache = tp.tileParams.icache.map(_.copy(nTLBWays = tlbways))))
-    case t => t
-  }
-})
-
-class WithL1DCacheTLBWays(tlbways: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(nTLBWays = tlbways))))
-    case t => t
-  }
-})
-
-class WithL1ICacheTLBBasePageSectors(pagesectors: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      icache = tp.tileParams.icache.map(_.copy(nTLBBasePageSectors = pagesectors))))
-    case t => t
-  }
-})
-
-class WithL1DCacheTLBBasePageSectors(pagesectors: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(nTLBBasePageSectors = pagesectors))))
-    case t => t
-  }
-})
-
-class WithL1ICacheTLBSuperpages(superpages: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      icache = tp.tileParams.icache.map(_.copy(nTLBSuperpages = superpages))))
-    case t => t
-  }
-})
-
-class WithL1DCacheTLBSuperpages(superpages: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(nTLBSuperpages = superpages))))
-    case t => t
-  }
-})
-
-class WithRocketICacheRowBits(n: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      icache = tp.tileParams.icache.map(_.copy(rowBits = n))))
-    case t => t
-  }
-})
-
-class WithRocketDCacheRowBits(n: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(rowBits = n))))
-    case t => t
-  }
-})
-
-class WithL1ICacheBlockBytes(bytes: Int = 64) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      icache = tp.tileParams.icache.map(_.copy(blockBytes = bytes))))
-    case t => t
-  }
-})
-
-class WithL1DCacheBlockBytes(bytes: Int = 64) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(blockBytes = bytes))))
-    case t => t
-  }
-})
-
-class WithoutVM extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(useVM = false)))
-    case t => t
-  }
-})
-
-class WithCFlushEnabled extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(haveCFlush = true)))
-    case t => t
-  }
-})
-
-class WithRocketCacheRowBits(n: Int) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(rowBits = n)),
-      icache = tp.tileParams.icache.map(_.copy(rowBits = n))))
-    case t => t
-  }
-})
-
 class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
   case CacheBlockBytes => linesize
 })
@@ -454,77 +143,22 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
   case BroadcastKey => up(BroadcastKey, site).copy(bufferless = true)
 })
 
-/**
- * WARNING!!! IGNORE AT YOUR OWN PERIL!!!
- *
- * There is a very restrictive set of conditions under which the stateless
- * bridge will function properly. There can only be a single tile. This tile
- * MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
- * uncached channel capable of writes (i.e. a RoCC accelerator).
- *
- * This is because the stateless bridge CANNOT generate probes, so if your
- * system depends on coherence between channels in any way,
- * DO NOT use this configuration.
- */
-class WithIncoherentTiles extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = tp.crossingParams.master match {
-        case x: HierarchicalElementMasterPortParams => x.copy(cork = Some(true))
-        case _ => throw new Exception("Unrecognized type for RocketCrossingParams.master")
-      }))
-    case t => t
-  }
-  case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(
-    coherenceManager = CoherenceManagerWrapper.incoherentManager
-  )
-})
-
-class WithRV32 extends Config((site, here, up) => {
-  case XLen => 32
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(
-        fpu = tp.tileParams.core.fpu.map(_.copy(fLen = 32)),
-        mulDiv = Some(MulDivParams(mulUnroll = 8)))))
-    case t => t
-  }
-})
-
-class WithFP16 extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(
-        fpu = tp.tileParams.core.fpu.map(_.copy(minFLen = 16))
-      )
-    ))
-    case t => t
-  }
-})
-
-class WithNonblockingL1(nMSHRs: Int) extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(nMSHRs = nMSHRs))))
-    case t => t
-  }
-})
-
-class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(nBreakpoints = hwbp)))
-    case t => t
-  }
-})
-
-class WithHypervisor(hext: Boolean = true) extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(useHypervisor = hext)))
-    case t => t
-  }
-})
+class TileAttachConfig[T <: CanAttachTile](f: T => T, locationOpt: Option[HierarchicalLocation], tileIdOpt: Seq[Int])(implicit tag: ClassTag[T])
+  extends Config((site, here, up) => {
+    val partialFn: PartialFunction[CanAttachTile, CanAttachTile] = { case tp: T => if (tileIdOpt.contains(tp.tileParams.tileId) || tileIdOpt.isEmpty) f(tp) else tp }
+    val alterFn: CanAttachTile => CanAttachTile = x => partialFn.applyOrElse(x, identity[CanAttachTile])
+    locationOpt match {
+      case Some(loc) => { case TilesLocated(`loc`) => up(TilesLocated(loc)) map { alterFn(_) } }
+      case None      => { case TilesLocated(loc)   => up(TilesLocated(loc)) map { alterFn(_) } }
+    }
+  }) {
+  // The default constructor applies the modification to all locations
+  def this(f: T => T)(implicit tag: ClassTag[T]) = this(f, None, Nil)
+  // The atLocation method applies the modification to only the provided location
+  def atLocation(loc: HierarchicalLocation) = new TileAttachConfig(f, Some(loc), tileIdOpt)
+  // The atTileIds method applies the modification only to specified tileIds
+  def atTileIds(ids: Int*) = new TileAttachConfig(f, locationOpt, tileIdOpt ++ ids)
+}
 
 class WithRoccExample extends Config((site, here, up) => {
   case BuildRoCC => List(
@@ -546,130 +180,30 @@ class WithRoccExample extends Config((site, here, up) => {
     })
 })
 
-class WithDefaultBtb extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      btb = Some(BTBParams())))
-    case t => t
-  }
-})
-
-class WithNoBtb extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      btb = None))
-    case t => t
-  }
-})
-
-class WithFastMulDiv extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(mulDiv = Some(
-        MulDivParams(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true)))))
-    case t => t
-  }
-})
-
-class WithCustomFastMulDiv(mUnroll: Int = 8, mEarlyOut: Boolean = true, dUnroll: Int = 1, dEarlyOut: Boolean = true, dEarlyOutGranularity: Int = 1) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(mulDiv = Some(
-        MulDivParams(mulUnroll = mUnroll, mulEarlyOut = mEarlyOut, divUnroll = dUnroll, divEarlyOut = dEarlyOut, divEarlyOutGranularity = dEarlyOutGranularity)))))
-    case t => t
-  }
-})
-
-class WithoutMulDiv extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(mulDiv = None)))
-    case t => t
-  }
-})
-
-class WithoutFPU extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(fpu = None)))
-    case t => t
-  }
-})
-
-class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
+/**
+ * WARNING!!! IGNORE AT YOUR OWN PERIL!!!
+ *
+ * There is a very restrictive set of conditions under which the stateless
+ * bridge will function properly. There can only be a single tile. This tile
+ * MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
+ * uncached channel capable of writes (i.e. a RoCC accelerator).
+ *
+ * This is because the stateless bridge CANNOT generate probes, so if your
+ * system depends on coherence between channels in any way,
+ * DO NOT use this configuration.
+ */
+class WithIncoherentTiles extends Config((site, here, up) => {
   case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(fpu = tp.tileParams.core.fpu.map(_.copy(divSqrt = false)))))
-    case t => t
-  }
-})
-
-class WithBEU(addr: BigInt) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(beuAddr = Some(addr)))
-    case t => t
-  }
-})
-
-class WithRocketTileCDC(crossingType: ClockCrossingType = SynchronousCrossing()) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      crossingType = crossingType
-    ))
-    case other => other
-  }
-})
-
-class WithSeperateClockReset extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      forceSeparateClockReset = true
-    ))
-    case other => other
-  }
-})
-
-
-class WithRocketDebugROB(enable: Boolean = true, size: Int = 0) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams if (enable) =>
-      tp.copy(tileParams = tp.tileParams.copy(
-        core = tp.tileParams.core.copy(debugROB = Some(DebugROBParams(size)))
-      ))
-  }
-})
-
-class WithRocketCease(enable: Boolean = true) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(haveCease = enable)
-    ))
-  }
-})
-
-class WithCoreClockGatingEnabled extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(clockGate = true)
-    ))
-    case t => t
-  }
-})
-
-class WithDCacheClockGatingEnabled extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(_.copy(clockGate = true))))
-    case t => t
-  }
-})
-
-class WithNoSimulationTimeout extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(haveSimTimeout = false)))
+      master = tp.crossingParams.master match {
+        case x: HierarchicalElementMasterPortParams => x.copy(cork = Some(true))
+        case _ => throw new Exception("Unrecognized type for RocketCrossingParams.master")
+      }))
     case t => t
   }
+  case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(
+    coherenceManager = CoherenceManagerWrapper.incoherentManager
+  )
 })
 
 class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
@@ -680,30 +214,6 @@ class WithClockGateModel(file: String = "/vsrc/EICG_wrapper.v") extends Config((
   case ClockGateModelFile => Some(file)
 })
 
-class WithSynchronousRocketTiles extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      crossingType = SynchronousCrossing()))
-    case t => t
-  }
-})
-
-class WithAsynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      crossingType = AsynchronousCrossing()))
-    case t => t
-  }
-})
-
-class WithRationalRocketTiles extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      crossingType = RationalCrossing()))
-    case t => t
-  }
-})
-
 class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
   case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8)
   case ExtIn => up(ExtIn, site).map(_.copy(beatBytes = dataBits/8))
@@ -809,29 +319,6 @@ class WithNoSlavePort extends Config((site, here, up) => {
   case ExtIn => None
 })
 
-class WithScratchpadsBaseAddress(address: BigInt) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      dcache = tp.tileParams.dcache.map(
-        _.copy(scratch = Some(address))
-      )
-    ))
-    case t => t
-  }
-})
-
-class WithScratchpadsOnly extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(useVM = false),
-      dcache = tp.tileParams.dcache.map(_.copy(
-        nSets = 256, // 16Kb scratchpad
-        nWays = 1,
-        scratch = Some(0x80000000L)))))
-    case t => t
-  }
-})
-
 /**
   * Mixins to specify crossing types between the 5 traditional TL buses
   *
@@ -880,26 +367,6 @@ class WithDontDriveBusClocksFromSBus extends Config((site, here, up) => {
   case DriveClocksFromSBus => false
 })
 
-class WithCloneRocketTiles(
-  n: Int = 1,
-  cloneTileId: Int = 0,
-  location: HierarchicalLocation = InSubsystem,
-  cloneLocation: HierarchicalLocation = InSubsystem
-) extends Config((site, here, up) => {
-  case TilesLocated(`location`) => {
-    val prev = up(TilesLocated(location), site)
-    val idOffset = up(NumTiles)
-    val tileAttachParams = up(TilesLocated(cloneLocation)).find(_.tileParams.tileId == cloneTileId)
-      .get.asInstanceOf[RocketTileAttachParams]
-    (0 until n).map { i =>
-      CloneTileAttachParams(cloneTileId, tileAttachParams.copy(
-        tileParams = tileAttachParams.tileParams.copy(tileId = i + idOffset)
-      ))
-    } ++ prev
-  }
-  case NumTiles => up(NumTiles) + n
-})
-
 class WithCloneCluster(
   clusterId: Int,
   cloneClusterId: Int = 0,
diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala
index 9827cf428c0..a78712c91ad 100644
--- a/src/main/scala/system/Configs.scala
+++ b/src/main/scala/system/Configs.scala
@@ -5,6 +5,7 @@ package freechips.rocketchip.system
 
 import org.chipsalliance.cde.config.Config
 import freechips.rocketchip.subsystem._
+import freechips.rocketchip.rocket.{WithNBigCores, WithNMedCores, WithNSmallCores, WithRV32, WithFP16, WithHypervisor, With1TinyCore, WithScratchpadsOnly, WithCloneRocketTiles}
 
 class WithJtagDTMSystem extends freechips.rocketchip.subsystem.WithJtagDTM
 class WithDebugSBASystem extends freechips.rocketchip.subsystem.WithDebugSBA
diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala
index 4520381887f..4e0c5d3b49d 100644
--- a/src/main/scala/tile/BaseTile.scala
+++ b/src/main/scala/tile/BaseTile.scala
@@ -12,7 +12,7 @@ import org.chipsalliance.diplomacy.bundlebridge._
 
 import freechips.rocketchip.resources.{PropertyMap, PropertyOption, ResourceReference, DTSTimebase}
 import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode}
-import freechips.rocketchip.rocket.{ICacheParams, DCacheParams, BTBParams, PgLevels, ASIdBits, VMIdBits, TraceAux, BPWatch}
+import freechips.rocketchip.rocket.{ICacheParams, DCacheParams, BTBParams, ASIdBits, VMIdBits, TraceAux, BPWatch}
 import freechips.rocketchip.subsystem.{
   HierarchicalElementParams, InstantiableHierarchicalElementParams, HierarchicalElementCrossingParamsLike,
   CacheBlockBytes, SystemBusKey, BaseHierarchicalElement, InsertTimingClosureRegistersOnHartIds, BaseHierarchicalElementModuleImp
@@ -61,12 +61,12 @@ trait HasNonDiplomaticTileParameters {
   def usingPTW: Boolean = usingVM
   def usingDataScratchpad: Boolean = tileParams.dcache.flatMap(_.scratch).isDefined
 
-  def xLen: Int = p(XLen)
+  def xLen: Int = tileParams.core.xLen
   def xBytes: Int = xLen / 8
   def iLen: Int = 32
   def pgIdxBits: Int = 12
   def pgLevelBits: Int = 10 - log2Ceil(xLen / 32)
-  def pgLevels: Int = p(PgLevels)
+  def pgLevels: Int = tileParams.core.pgLevels
   def maxSVAddrBits: Int = pgIdxBits + pgLevels * pgLevelBits
   def maxHypervisorExtraAddrBits: Int = 2
   def hypervisorExtraAddrBits: Int = {
@@ -128,7 +128,7 @@ trait HasNonDiplomaticTileParameters {
       tileParams.core.customIsaExt.map(Seq(_))
     ).flatten
     val multiLetterString = multiLetterExt.mkString("_")
-    s"rv${p(XLen)}$ie$m$a$f$d$c$v$h$multiLetterString"
+    s"rv$xLen$ie$m$a$f$d$c$v$h$multiLetterString"
   }
 
   def tileProperties: PropertyMap = {
diff --git a/src/main/scala/tile/BusErrorUnit.scala b/src/main/scala/tile/BusErrorUnit.scala
index bbfe3fb3628..850550afb80 100644
--- a/src/main/scala/tile/BusErrorUnit.scala
+++ b/src/main/scala/tile/BusErrorUnit.scala
@@ -36,14 +36,14 @@ class L1BusErrors(implicit p: Parameters) extends CoreBundle()(p) with BusErrors
 
 case class BusErrorUnitParams(addr: BigInt, size: Int = 4096)
 
-class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit p: Parameters) extends LazyModule {
+class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule {
   val regWidth = 64
   val device = new SimpleDevice("bus-error-unit", Seq("sifive,buserror0"))
   val intNode = IntSourceNode(IntSourcePortSimple(resources = device.int))
   val node = TLRegisterNode(
     address   = Seq(AddressSet(params.addr, params.size-1)),
     device    = device,
-    beatBytes = p(XLen)/8)
+    beatBytes = beatBytes)
 
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala
index 449af093b0c..603eba21523 100644
--- a/src/main/scala/tile/Core.scala
+++ b/src/main/scala/tile/Core.scala
@@ -8,7 +8,6 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.util._
 
-case object XLen extends Field[Int]
 case object MaxHartIdBits extends Field[Int]
 
 // These parameters can be varied per-core
@@ -51,6 +50,8 @@ trait CoreParams {
   val mtvecInit: Option[BigInt]
   val mtvecWritable: Boolean
   val traceHasWdata: Boolean
+  val xLen: Int
+  val pgLevels: Int
   def traceCustom: Option[Data] = None
   def customIsaExt: Option[String] = None
   def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs
@@ -120,6 +121,14 @@ trait HasCoreParameters extends HasTileParameters {
     require(vfLen <= eLen)
   }
 
+  if (coreParams.useVM) {
+    if (coreParams.xLen == 32) {
+      require(coreParams.pgLevels == 2)
+    } else {
+      require(coreParams.pgLevels >= 3)
+    }
+  }
+
   lazy val hartIdLen: Int = p(MaxHartIdBits)
   lazy val resetVectorLen: Int = {
     val externalLen = paddrBits
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index 42cf9b644ed..619e7d836ca 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -77,7 +77,7 @@ class RocketTile private(
   dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes))
 
   val bus_error_unit = rocketParams.beuAddr map { a =>
-    val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
+    val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a), xLen/8))
     intOutwardNode.get := beu.intNode
     connectTLSlave(beu.node, xBytes)
     beu