[JIT] Emulation Error Aarch64 bics

[echarron-git]

Hello,

I have not the same result with a native CPU and MIASM (miasm==0.1.5.dev47) for the following instruction "5f 03 28 6a" interpreted by MIASM as bics wsp,w26,w8 and not bics wzr,w26,w8 (Zero Register)

From my understanding only register flag should be updated not WSP. Below the snippet to play again the bug

def hook_end(jitter):
    return False

loc_db = LocationDB()
machine = Machine("aarch64l")
jitter = machine.jitter(loc_db, jit_type="python")
jitter.vm.add_memory_page(0x791CD31C78, PAGE_READ | PAGE_WRITE | PAGE_EXEC, b'\x5f\x03\x28\x6a\xc1\x03\x00\x54' , "CODE")

jitter.add_breakpoint(0x791CD31C7C, hook_end) # hook_End
jitter.set_trace_log()

jitter.cpu.SP   = 0x000075EF98DD10
jitter.cpu.X26  = 0x0000000000004200
jitter.cpu.X8   = 0x00000000000208
jitter.run(0x791CD31C78)

I would be very grateful if anyone could correct the problem.