diff --git a/mtkcpu/tests/test_csr.py b/mtkcpu/tests/test_csr.py
index b30d2dc..efb0a83 100644
--- a/mtkcpu/tests/test_csr.py
+++ b/mtkcpu/tests/test_csr.py
@@ -284,33 +284,6 @@
 ]
 
 EXDI = [
-    # MemTestCase(
-    #     name="TEST test TEST",
-    #     source_type=MemTestSourceType.RAW,
-    #     source=f"""
-    #         start:
-    #             la x5, trap
-    #             csrw mtvec, x5
-    #             li x1, 0b1000  # mstatus.mie
-    #             csrw mstatus, x1
-    #             li x1, 0b10000000 # mie.mtie
-    #             csrw mie, x1
-    #         loop:
-    #             j loop
-    #         trap:
-    #             csrr x1, mepc
-    #             addi x1, x1, 4
-    #             csrw mepc, x1
-    #             mret
-    #             addi x2, x0, 10
-    #     """,
-    #     out_reg=2,
-    #     out_val=20,
-    #     timeout=100,
-    #     mem_init=MemoryContents.empty(),
-    #     reg_init=RegistryContents.fill(),
-    # ),
-
     MemTestCase(
         name="timer interrupt",
         source_type=MemTestSourceType.RAW,
@@ -330,10 +303,11 @@
             loop:
                 j loop
             trap:
-                addi x15, x0, 123
+                csrr x14, mcause
+                andi x15, x14, 0xff
         """,
         out_reg=15,
-        out_val=123,
+        out_val=IrqCause.M_TIMER_INTERRUPT,
         timeout=2000,
         mem_init=MemoryContents.empty(),
         reg_init=RegistryContents.fill(),