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Add fusesoc handler #8

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benreynwar opened this issue Sep 28, 2018 · 0 comments
Open

Add fusesoc handler #8

benreynwar opened this issue Sep 28, 2018 · 0 comments

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@benreynwar
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It'd be cool if fusesoc exposed a board-independent and vendor-independent way of communicating with FPGAs. Then axilent could use these methods to run the simulation on an FPGA. To start off with it makes sense to move the functionality currently in pyvivado into fusesoc.
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@benreynwar