Fix design/code to adhere to modern standards

[SZBihan]

See the uart_rx.v and uart_tx.v files (in rtl folder). They use parameters before declaring them. This is unacceptable by modern Verilog standards, even for Iverilog. As is, the compilation fails (for current Iverilog).

I suggest making such ones module parameters:
module #(parameter ...) ...

This fixes the issue