feat(vector) Implemented vector operation formats.

Author: x4exr

examples/counter.rs

@@ -0,0 +1,19 @@
+extern crate arrseq_lightning;
+
+use arrseq_lightning::instruction::{Instruction, memory};
+use arrseq_lightning::instruction::register::Register;
+use arrseq_lightning::num::Size;
+
+fn main() {
+    let program = [
+        Instruction::Memory {
+            operation: memory::Operation::AddressedCopy,
+            size: Size::X8,
+            register: Register::new(0),
+            address: memory::Address::Immediate { 
+                mode: memory::Mode::Absolute,
+                immediate: 0
+            }
+        }
+    ];
+}

src/instruction.rs

@@ -22,6 +22,15 @@ pub enum DualSizedRegisterOperation {
 
 }
 
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum DualArithmetic {}
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum TriArithmetic {}
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum QuadArithmetic {}
+
 #[derive(Debug, Clone, Copy, PartialEq)]
 pub enum Instruction {
     Nothing,
@@ -33,12 +42,37 @@ pub enum Instruction {
     DualSizedRegister {
         operation: DualSizedRegisterOperation,
         size: num::Size, registers: [Register; 2] },
+    DualArithmetic {
+        operation: DualArithmetic,
+        vector: bool, size: num::Size,
+        registers: [Register; 2] },
+    TriArithmetic {
+        operation: TriArithmetic,
+        vector: bool, size: num::Size,
+        registers: [Register; 3] },
+    QuadArithmetic {
+        operation: QuadArithmetic,
+        vector: bool, size: num::Size,
+        registers: [Register; 4] },
+    LoadImmediate {
+        immediate: u16, segment: num::MaskedU8<0x03> },
     Branch {
         operation: branch::Operation,
         condition: Option<Flag>, hint: branch::Hint,
         address: branch::Address },
     Memory {
         operation: memory::Operation,
         size: num::Size, register: Register,
-        address: memory::Address }
+        address: memory::Address },
+    LoadVector {
+        vector: Register,
+        components: [Option<Register>; 4], 
+        persist: bool },
+    ReorderVector {
+        vector: Register,
+        components: [num::MaskedU8<0x03>; 4],
+        persist: bool },
+    SplitVector {
+        vector: Register,
+        components: [Option<Register>; 4] }
 }

src/instruction/memory.rs

@@ -3,7 +3,8 @@ use crate::num;
 
 #[derive(Debug, Clone, Copy, PartialEq)]
 pub enum Operation {
-
+    CopyRegister,
+    CopyAddressed
 }
 
 #[derive(Debug, Clone, Copy, PartialEq)]

src/instruction/register.rs

@@ -1,4 +1,4 @@
 use crate::num;
 
-pub const REGISTER_MASK: u8 = 0x03;
+pub const REGISTER_MASK: u8 = 0x0F;
 pub type Register = num::MaskedU8<REGISTER_MASK>;

src/lib.rs

@@ -16,5 +16,4 @@
 
 pub mod instruction;
 pub mod num;
-pub mod operation;
-pub mod state;
+pub mod operation;