feat(v2foxy) Updated instruction to support foxy.

Author: x4exr

examples/counter.rs

@@ -2,7 +2,7 @@ extern crate arrseq_lightning;
 
 use arrseq_lightning::instruction::{address, Instruction, operation, RegisterCode};
 use arrseq_lightning::instruction::address::{Address};
-use arrseq_lightning::instruction::flag::Flag;
+use arrseq_lightning::instruction::branch::Flag;
 use arrseq_lightning::num::MaskedU8;
 
 fn main() {

src/instruction.rs

@@ -1,106 +1,86 @@
-pub mod operation;
+use crate::instruction::address::{AccessMode, Address};
+use crate::num::{MaskedU32, MaskedU8};
+
 pub mod address;
 pub mod vector;
-pub mod flag;
+pub mod branch;
 pub mod encoding;
-
-use crate::instruction::address::Address;
-use crate::instruction::flag::Flag;
-use crate::num::{MaskedU8};
+mod register;
+mod arithmetic;
 
 pub type SegmentCode = MaskedU8<0x3>;
-pub type RegisterCode = MaskedU8<0xF>;
-pub type BranchHintCode = MaskedU8<0x3>;
-pub type OperandCode = MaskedU8<0x3>;
-
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub enum Format {
-    WaitForInterrupt,
-    LoadImmediate,
-    LoadVectorComponents,
-    ExtractVectorComponents,
-    MapVector,
-    Branch,
-    DualSource(operation::DualSource),
-    Destination(operation::Destination),
-    DestinationSource(operation::DestinationSource),
-    DestinationDualSource(operation::DestinationDualSource),
-    DestinationTripleSource(operation::DestinationTripleSource),
-    DualDestinationDualSource(operation::DualDestinationDualSource),
-    Memory(operation::Memory),
-    SourceMemory(operation::SourceMemory),
-    DestinationMemory(operation::DestinationMemory)
-}
+pub type LargeImmediate = MaskedU32<0x1FFFFF>;
+pub type ScaleCode = MaskedU8<0x03>;
 
 #[derive(Debug, Clone, Copy, PartialEq)]
 pub enum Instruction {
-    WaitForInterrupt,
-    LoadImmediate {
-        destination: RegisterCode,
+    None,
+    Wait,
+    
+    End,
+    EndInterrupt,
+    Interrupt,
+    
+    Stack { source: register::Code },
+    Unstack { destination: register::Code },
+    
+    LoadImmediate { 
+        destination: register::Code,
         segment: SegmentCode,
-        immediate: u16
-    },
-    LoadVectorComponents {
-        destination: RegisterCode,
-        /// Having [None] means that the component corresponding to the index should be 0.
-        components: [Option<RegisterCode>; vector::SIZE]
+        immediate: LargeImmediate
     },
-    ExtractVectorComponents {
-        source: RegisterCode,
-        /// Having [None] means that the component corresponding to the index should not be extracted into a register.
-        destinations: [Option<RegisterCode>; vector::SIZE]
+    BuildVector {
+        destination: register::Code,
+        components: [register::Code; vector::SIZE]
     },
-    /// Only supports 2 operands due to the size constrain of an instruction.
-    MapVector {
-        temporary: bool,
-        operand: OperandCode,
-        mappings: [vector::ComponentCode; vector::SIZE]
+    UnBuildVector {
+        source: register::Code,
+        destinations: [register::Code; vector::SIZE]
     },
-    Branch {
-        condition: Flag,
-        hint: Option<bool>,
-        address: Address
-    },
-    DualSource {
-        operation: operation::DualSource,
-        sources: [RegisterCode; 2]
-    },
-    Destination {
-        operation: operation::Destination,
-        destination: RegisterCode
+    
+    CopyRegister {
+        destination: register::Code,
+        destination_file: register::FileName,
+        source: register::Code,
+        source_file: register::FileName
     },
-    DestinationSource {
-        operation: operation::DestinationSource,
-        destination: RegisterCode,
-        source: RegisterCode
+    
+    Arithmetic {
+        operation: arithmetic::Operation,
+        vector: bool,
+        atomic: bool,
+        destination: register::Code,
+        sources: [register::Code; 2]
     },
-    DestinationDualSource {
-        operation: operation::DestinationDualSource,
-        destination: RegisterCode,
-        sources: [RegisterCode; 2]
+    Address {
+        operation: address::Operation,
+        data: address::Meta,
+        offset: address::LargeOffset
     },
-    DestinationTripleSource {
-        operation: operation::DestinationTripleSource,
-        destination: RegisterCode,
-        sources: [RegisterCode; 3]
+    AddressWithBase {
+        operation: address::OperationWithBase,
+        data: address::Meta,
+        base: register::Code,
+        offset: address::SmallOffset
     },
-    DualDestinationDualSource {
-        operation: operation::DualDestinationDualSource,
-        destinations: [RegisterCode; 2], 
-        sources: [RegisterCode; 2]
-    },
-    Memory {
-        operation: operation::Memory,
-        address: Address
+    Branch {
+        operation: branch::Operation,
+        data: branch::Meta,
+        offset: branch::LargeOffset
     },
-    SourceMemory {
-        operation: operation::SourceMemory,
-        destination: RegisterCode,
-        source: Address
+    BranchWithBase {
+        operation: branch::OperationWithBase,
+        data: branch::Meta,
+        base: register::Code,
+        offset: branch::SmallOffset
     },
-    DestinationMemory {
-        operation: operation::DestinationMemory,
-        destination: Address,
-        source: RegisterCode
-    }
+    
+    Timer,
+    
+    Lock,
+    UnLock,
+    
+    Free2,
+    Free3,
+    Free4
 }

src/instruction/address.rs

@@ -1,46 +1,24 @@
-use crate::instruction::RegisterCode;
-use crate::num::{MaskedU16, MaskedU32, MaskedU8};
-
-pub type LargeImmediate = MaskedU32<0x1FFFF>;
-pub type ScaleCode = MaskedU8<0x3>;
+use crate::instruction::{register, ScaleCode};
+use crate::num::MaskedU32;
 
 #[derive(Debug, Clone, Copy, PartialEq)]
-pub enum Mode {
-    Absolute,
-    Relative
+pub enum AccessMode {
+    Read,
+    Write
 }
 
-pub type MediumImmediate = MaskedU16<0x1FFF>;
-pub type ShortImmediate = MaskedU16<0x1FF>;
+pub type LargeOffset = MaskedU32<0xFFFFF>;
+pub type SmallOffset = MaskedU32<0x3FFF>;
 
 #[derive(Debug, Clone, Copy, PartialEq)]
-pub enum IndexedBaseOffsetMode {
-    Immediate(ShortImmediate),
-    Register(RegisterCode)
+pub struct Meta {
+    pub relative: bool,
+    pub access_mode: AccessMode,
+    pub scale: ScaleCode,
 }
 
 #[derive(Debug, Clone, Copy, PartialEq)]
-pub enum BaseMode {
-    Offset(MediumImmediate),
-    RegisterOffset(RegisterCode),
-    Indexed {
-        index: RegisterCode,
-        offset: IndexedBaseOffsetMode
-    }
-}
+pub enum Operation {}
 
 #[derive(Debug, Clone, Copy, PartialEq)]
-pub enum Address {
-    Immediate {
-        mode: Mode,
-        immediate: LargeImmediate
-    },
-    Register {
-        mode: Mode,
-        register: RegisterCode
-    },
-    Base {
-        mode: BaseMode,
-        base: RegisterCode
-    }
-}
+pub enum OperationWithBase {}

src/instruction/arithmetic.rs

@@ -0,0 +1,7 @@
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum Operation {
+    Add,
+    Subtract,
+    Multiply,
+    Divide
+}

src/instruction/branch.rs

@@ -0,0 +1,28 @@
+use crate::num::{MaskedU32, MaskedU8};
+
+pub type Code = MaskedU8<0x07>;
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum Flag {
+    Zero,
+    Negative,
+    Overflow,
+    Regrouping,
+    Parity
+}
+
+pub type LargeOffset = MaskedU32<0x1FFFFFF>;
+pub type SmallOffset = MaskedU32<0xFFFFF>;
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub struct Meta {
+    pub relative: bool,
+    pub call: bool,
+    pub demote: bool,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum Operation {}
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum OperationWithBase {}