feat(counter) Implemented basic counter program for emulation testing.

Author: x4exr

examples/counter.rs

@@ -1,9 +1,28 @@
 extern crate arrseq_lightning;
 
-use arrseq_lightning::instruction::Instruction;
+use arrseq_lightning::instruction::{address, Instruction, operation, RegisterCode};
+use arrseq_lightning::instruction::address::{Address};
+use arrseq_lightning::instruction::flag::Flag;
+use arrseq_lightning::num::MaskedU8;
 
 fn main() {
+    let c_max = 10u16;
+    
     let program = [
-        Instruction::
+        Instruction::LoadImmediate { destination: RegisterCode::new(0), segment: MaskedU8::new(0), immediate: c_max },                                              // li r0, c_max
+        Instruction::DualSource { operation: operation::DualSource::Compare, sources: [RegisterCode::new(0), RegisterCode::new(1)] },                               // cmp r0, r1
+        Instruction::Branch { hint: None, condition: Flag::Zero, address: Address::Immediate { immediate: address::Immediate::new(8), mode: address::Mode::Relative }},    // jz pc+8
+        Instruction::Memory { operation: operation::Memory::Branch, address: Address::Immediate { immediate: address::Immediate::new(4), mode: address::Mode::Absolute }}, // jmp 0
+        Instruction::WaitForInterrupt                                                                                                                                             // hlt
+        
+        // pseudo code:
+        // 
+        // ```
+        // let count = c_max;
+        // loop {
+        //     count -= 1;
+        //     if count == 0 { return 0 }
+        // }
+        // ```
     ];
 }

src/operation.rs src/core.rs

@@ -1,81 +1,29 @@
 pub mod operation;
+pub mod address;
+pub mod vector;
+pub mod flag;
 
-use crate::num::{MaskedU16, MaskedU32, MaskedU8};
+use crate::instruction::address::Address;
+use crate::instruction::flag::Flag;
+use crate::instruction::vector::{VectorComponentFlags, VectorComponentMapping};
+use crate::num::{MaskedU8};
 
-pub type SegmentCode = MaskedU8<0x3>
+pub type SegmentCode = MaskedU8<0x3>;
 pub type RegisterCode = MaskedU8<0xF>;
-pub type FlagCode = MaskedU8<0x07>;
 pub type BranchHintCode = MaskedU8<0x3>;
 pub type OperandCode = MaskedU8<0x3>;
-pub type VectorComponentCode = MaskedU8<0x3>;
-pub const VECTOR_SIZE: usize = 4;
-
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub struct VectorComponentMapping {
-    operand: OperandCode,
-    components: [VectorComponentCode; 2]
-}
-
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub struct VectorComponentFlags {
-    operand: OperandCode,
-    negate: bool,
-    zero: bool
-}
-
-pub type AddressImmediate = MaskedU32<0x1FFFF>;
-pub type ScaleCode = MaskedU8<0x3>;
-
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub enum AddressMode {
-    Absolute,
-    Relative
-}
-
-pub type BaseOffset = MaskedU16<0x1FFF>;
-pub type IndexedBaseOffset = MaskedU16<0x1FF>;
-
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub enum IndexedBaseOffsetMode {
-    Immediate(IndexedBaseOffset),
-    Register(RegisterCode)
-}
-
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub enum BaseMode {
-    Offset(BaseOffset),
-    RegisterOffset(RegisterCode),
-    Indexed {
-        index: RegisterCode,
-        offset: IndexedBaseOffsetMode
-    }
-}
-
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub enum Address {
-    Immediate {
-        immediate: AddressImmediate,
-        mode: AddressMode
-    },
-    Register {
-        register: RegisterCode,
-        mode: AddressMode
-    },
-    Base {
-        base: RegisterCode, 
-        mode: BaseMode
-    }
-}
 
 #[derive(Debug, Clone, Copy, PartialEq)]
 pub enum Instruction {
+    WaitForInterrupt,
     LoadImmediate {
+        destination: RegisterCode,
         segment: SegmentCode,
         immediate: u16
     },
     DualSource {
         operation: operation::DualSource,
-        source: [RegisterCode; 2]
+        sources: [RegisterCode; 2]
     },
     Destination {
         operation: operation::Destination,
@@ -104,15 +52,15 @@ pub enum Instruction {
     LoadVectorComponents {
         destination: RegisterCode,
         /// Having [None] means that the component corresponding to the index should be 0.
-        components: [Option<VectorComponentCode>; VECTOR_SIZE]
+        components: [Option<vector::ComponentCode>; vector::SIZE]
     },
     ExtractVectorComponents {
         vector: RegisterCode,
         /// Having [None] means that the component corresponding to the index should not be extracted into a register.
-        components: [Option<RegisterCode>; VECTOR_SIZE]
+        components: [Option<RegisterCode>; vector::SIZE]
     },
     FlagVectorComponents {
-        flags: [VectorComponentFlags; VECTOR_SIZE],
+        flags: [VectorComponentFlags; vector::SIZE],
         temporary: bool
     },
     /// Only supports 2 operands due to the size constrain of an instruction.
@@ -135,7 +83,7 @@ pub enum Instruction {
         source: RegisterCode
     },
     Branch {
-        condition: FlagCode,
+        condition: Flag,
         hint: Option<bool>,
         address: Address
     }

src/instruction.rs

@@ -0,0 +1,46 @@
+use crate::instruction::RegisterCode;
+use crate::num::{MaskedU16, MaskedU32, MaskedU8};
+
+pub type Immediate = MaskedU32<0x1FFFF>;
+pub type ScaleCode = MaskedU8<0x3>;
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum Mode {
+    Absolute,
+    Relative
+}
+
+pub type BaseOffset = MaskedU16<0x1FFF>;
+pub type IndexedBaseOffset = MaskedU16<0x1FF>;
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum IndexedBaseOffsetMode {
+    Immediate(IndexedBaseOffset),
+    Register(RegisterCode)
+}
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum BaseMode {
+    Offset(BaseOffset),
+    RegisterOffset(RegisterCode),
+    Indexed {
+        index: RegisterCode,
+        offset: IndexedBaseOffsetMode
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum Address {
+    Immediate {
+        immediate: Immediate,
+        mode: Mode
+    },
+    Register {
+        register: RegisterCode,
+        mode: Mode
+    },
+    Base {
+        base: RegisterCode,
+        mode: BaseMode
+    }
+}

src/instruction/address.rs

@@ -0,0 +1,12 @@
+use crate::num::MaskedU8;
+
+pub type Code = MaskedU8<0x07>;
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub enum Flag {
+    Zero,
+    Negative,
+    Overflow,
+    Regrouping,
+    Parity
+}

src/instruction/flag.rs

@@ -1,7 +1,5 @@
 //! Enums of all operations for specific operand formats.
 
-use crate::instruction::Instruction;
-
 #[derive(Debug, Clone, Copy, PartialEq)]
 pub enum DualSource {
     Compare
@@ -42,8 +40,8 @@ pub enum DestinationDualSource {
 
 #[derive(Debug, Clone, Copy, PartialEq)]
 pub enum DestinationTripleSource {
-    MultiplyAndAdd, // mad
-    AddAndMultiply // adm
+    MultiplyAndAdd,
+    AddAndMultiply
 }
 
 #[derive(Debug, Clone, Copy, PartialEq)]
@@ -57,7 +55,8 @@ pub enum DualDestinationDualSource {
 #[derive(Debug, Clone, Copy, PartialEq)]
 pub enum Memory {
     Call,
-    ReleaseMemory
+    ReleaseMemory,
+    Branch
 }
 
 #[derive(Debug, Clone, Copy, PartialEq)]
@@ -66,7 +65,7 @@ pub enum SourceMemory {
     CopyMemoryWordToRegister,
     CopyMemoryDwordToRegister,
     CopyMemoryQwordToRegister,
-    
+
     AcquireMemoryByte,
     AcquireMemoryWord,
     AcquireMemoryDword,

src/instruction/operation.rs

@@ -0,0 +1,18 @@
+use crate::instruction::{OperandCode};
+use crate::num::MaskedU8;
+
+pub type ComponentCode = MaskedU8<0x3>;
+pub const SIZE: usize = 4;
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub struct VectorComponentMapping {
+    operand: OperandCode,
+    components: [ComponentCode; 2]
+}
+
+#[derive(Debug, Clone, Copy, PartialEq)]
+pub struct VectorComponentFlags {
+    operand: OperandCode,
+    negate: bool,
+    zero: bool
+}

src/instruction/vector.rs

@@ -14,8 +14,6 @@
 #![allow(clippy::unused_io_amount)]
 #![allow(soft_unstable)]
 
-// 
 pub mod instruction;
 pub mod num;
-// pub mod operation;
-// mod processor;
+pub mod core;