feat(encoding) Implemented encoding protocol for many instructions.

Author: x4exr

encoder_table.svg

@@ -1,25 +1,8 @@
 extern crate arrseq_lightning;
 
-use arrseq_lightning::instruction::{Instruction, LargeImmediate, register, SegmentCode};
-use arrseq_lightning::instruction::load_immediate::{Immediate, Segment};
+use arrseq_lightning::instruction::Instruction;
 
 fn main() {
-    let c_max = 10u16;
-
-    let program = [
-        Instruction::LoadImmediate {
-            destination: register::Code::new(0),
-            segment: Segment::Segment0(Immediate::new(c_max as u32))
-        }                                                                                                                                    // hlt
-
-        // pseudo code:
-        //
-        // ```
-        // let count = c_max;
-        // loop {
-        //     count -= 1;
-        //     if count == 0 { return 0 }
-        // }
-        // ```
-    ];
+    let ins = Instruction::decode(0b00000000_00000000_00000000_00000100);
+    dbg!(ins);
 }

examples/counter.rs

@@ -1,108 +1,79 @@
+use proc_bitfield::{bitfield, ConvRaw};
 use crate::num::MaskedU8;
 
-pub mod address;
-pub mod vector;
-pub mod branch;
-pub mod encoding;
-pub mod register;
-pub mod arithmetic;
 pub mod load_immediate;
+pub mod memory;
+pub mod mnemonic;
+pub mod vector;
 
-pub type SegmentCode = MaskedU8<0x3>;
-pub type ScaleCode = MaskedU8<0x03>;
-
-pub const STACK_SOURCE_MASK: (u8, u32) = (0, 0b0000000000000000000000011111);
-pub const UNSTACK_DEST_MASK: (u8, u32) = (0, 0b0000000000000000000000011111);
-
-pub const LOAD_IMMEDIATE_DESTINATION_MASK: (u8, u32) = (0, 0b0000000000000000000000011111);
-pub const LOAD_IMMEDIATE_SEGMENT_MASK    : (u8, u32) = (5, 0b0000000000000000000001100000);
-pub const LOAD_IMMEDIATE_OFFSET_MASK     : (u8, u32) = (7, 0b1111111111111111111110000000);
-
-pub const BUILD_VECTOR_DESTINATION_MASK: (u8, u32) = (0,  0b0000000000000000000000011111);
-pub const BUILD_VECTOR_COMPONENT_0_MASK: (u8, u32) = (5,  0b0000000000000000001111100000);
-pub const BUILD_VECTOR_COMPONENT_1_MASK: (u8, u32) = (10, 0b0000000000000111110000000000);
-pub const BUILD_VECTOR_COMPONENT_2_MASK: (u8, u32) = (15, 0b0000000011111000000000000000);
-pub const BUILD_VECTOR_COMPONENT_3_MASK: (u8, u32) = (20, 0b0001111100000000000000000000);
-
-pub const UNBUILD_VECTOR_SOURCE_MASK       : (u8, u32) = (0,  0b0000000000000000000000011111);
-pub const UNBUILD_VECTOR_DESTINATION_0_MASK: (u8, u32) = (5,  0b0000000000000000001111100000);
-pub const UNBUILD_VECTOR_DESTINATION_1_MASK: (u8, u32) = (10, 0b0000000000000111110000000000);
-pub const UNBUILD_VECTOR_DESTINATION_2_MASK: (u8, u32) = (15, 0b0000000011111000000000000000);
-pub const UNBUILD_VECTOR_DESTINATION_3_MASK: (u8, u32) = (20, 0b0001111100000000000000000000);
+bitfield! {
+    /// A bitfield showcasing how to specify bit ranges.
+    #[derive(Clone, Copy, PartialEq, Eq)]
+    struct Format(pub u32): Debug, FromRaw, IntoRaw { operation: u8 @ 0..=4 }
+}
 
-pub const COPY_REGISTER_DESTINATION_FILE_MASK: (u8, u32) = (0,  0b0000000000000000000000000011);
-pub const COPY_REGISTER_DESTINATION_MASK     : (u8, u32) = (0,  0b0000000000000000000001111100);
-pub const COPY_REGISTER_SOURCE_FILE_MASK     : (u8, u32) = (0,  0b0000000000000000000110000000);
-pub const COPY_REGISTER_SOURCE_MASK          : (u8, u32) = (0,  0b0000000000000011111000000000);
+#[derive(Debug, Clone, Copy, PartialEq, ConvRaw)]
+pub enum Scale { X8, X16, X32, X64 }
 
 #[derive(Debug, Clone, Copy, PartialEq)]
+#[repr(u8)]
 pub enum Instruction {
-    None,
-    Wait,
-    
-    End,
-    EndInterrupt,
-    Interrupt,
-    
-    Stack { source: register::Code },
-    Unstack { destination: register::Code },
-    
-    LoadImmediate { 
-        destination: register::Code,
-        segment: load_immediate::Segment
-    },
-    BuildVector {
-        destination: register::Code,
-        components: [register::Code; vector::SIZE]
-    },
-    UnBuildVector {
-        source: register::Code,
-        destinations: [register::Code; vector::SIZE]
-    },
-    
-    CopyRegister {
-        destination: register::Code,
-        destination_file: register::FileName,
-        source: register::Code,
-        source_file: register::FileName
-    },
+    Mnemonic(mnemonic::Operation),
+
+    LoadImmediate(load_immediate::Operation),
+    BuildVector(vector::BuildVectorOperation),
+    UnBuildVector(vector::UnBuildVectorOperation),
 
-    Arithmetic {
-        operation: arithmetic::Operation,
-        vector: bool,
-        atomic: bool,
-        destination: register::Code,
-        sources: [register::Code; 2]
-    },
-    Address {
-        operation: address::Operation,
-        data: address::Meta,
-        offset: address::LargeOffset
-    },
-    AddressWithBase {
-        operation: address::OperationWithBase,
-        data: address::Meta,
-        base: register::Code,
-        offset: address::SmallOffset
-    },
-    Branch {
-        operation: branch::Operation,
-        data: branch::Meta,
-        offset: branch::LargeOffset
-    },
-    BranchWithBase {
-        operation: branch::OperationWithBase,
-        data: branch::Meta,
-        base: register::Code,
-        offset: branch::SmallOffset
-    },
+    ReadMemory(memory::ReadOperation),
+    WriteMemory(memory::WriteOperation),
+    Stack(memory::StackOperation),
+    UnStack(memory::UnStackOperation),
+    Lock(memory::LockOperation),
+    Branch(memory::BranchOperation),
 
-    Timer,
+    Copy,
 
-    Lock,
-    UnLock,
+    Unary,
+    Negate,
+    SignExtend,
+    Binary,
+    RegroupingBinary,
+    RegroupingQuaternary
+}
+
+impl Instruction {
+    pub const MNEMONIC_CODE      : u8 = 0;
+    pub const LOAD_IMMEDIATE_CODE: u8 = 1;
+    pub const BUILD_VECTOR_CODE  : u8 = 2;
+    pub const UNBUILD_VECTOR_CODE: u8 = 3;
+    pub const READ_MEMORY_CODE   : u8 = 4;
+    pub const WRITE_MEMORY_CODE  : u8 = 5;
+    pub const STACK_CODE         : u8 = 6;
+    pub const UNSTACK_CODE       : u8 = 7;
+    pub const LOCK_CODE          : u8 = 8;
+    pub const BRANCH_CODE        : u8 = 9;
 
-    Free2,
-    Free3,
-    Free4
+    pub fn decode(encoded: u32) -> Self {
+        let operation = Format::from(encoded);
+        match operation.operation() {
+            Self::MNEMONIC_CODE => Self::Mnemonic(mnemonic::Format::from(encoded).operation()),
+            Self::LOAD_IMMEDIATE_CODE => Self::LoadImmediate(load_immediate::Operation::from(encoded)),
+            Self::BUILD_VECTOR_CODE => Self::BuildVector(vector::BuildVectorOperation::from(encoded)),
+            Self::UNBUILD_VECTOR_CODE => Self::UnBuildVector(vector::UnBuildVectorOperation::from(encoded)),
+            Self::READ_MEMORY_CODE => Self::ReadMemory(memory::ReadOperation::from(encoded)),
+            Self::WRITE_MEMORY_CODE => Self::WriteMemory(memory::WriteOperation::from(encoded)),
+            Self::STACK_CODE => Self::Stack(memory::StackOperation::from(encoded)),
+            Self::UNSTACK_CODE => Self::UnStack(memory::UnStackOperation::from(encoded)),
+            Self::LOCK_CODE => Self::Lock(memory::LockOperation::from(encoded)),
+            Self::BRANCH_CODE => Self::Branch(memory::BranchOperation::from(encoded)),
+
+            _ => unimplemented!()
+        }
+    }
+}
+
+impl Default for Instruction {
+    fn default() -> Self {
+        Self::Mnemonic(mnemonic::Operation::default())
+    }
 }

src/core.rs

@@ -1,11 +1,10 @@
-use crate::num::MaskedU32;
+use proc_bitfield::bitfield;
 
-pub type Immediate = MaskedU32<0x1FFFFF>;
-
-#[derive(Debug, Clone, Copy, PartialEq)]
-pub enum Segment {
-    Segment0(Immediate),
-    Segment1(Immediate),
-    Segment2(Immediate),
-    Segment3(bool)
+bitfield! {
+    #[derive(Clone, Copy, PartialEq, Eq)]
+    pub struct Operation(pub u32): Debug, FromRaw, IntoRaw { 
+        pub segment: u8 @ 5..=6,
+        pub value: u16 @ 11..=26,
+        pub base: u8 @ 27..=31
+    }
 }