From 64ae4974ae91de0308d9327b7276bf3dfc6ab4e8 Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Mon, 7 Oct 2024 14:06:30 +0200 Subject: [PATCH] Unsynthetizable types in inside expr riscv-dv/src/isa/riscv_instr.sv:157:57: Unsupported: RHS of ==? or !=? must be constant to be synthesizable : ... note: In instance 'riscv_instr_gen_tb_top' 157 | if (RV32C inside {riscv_instr_pkg::supported_isa[i]} && | ^ Signed-off-by: Ryszard Rozak --- src/isa/riscv_instr.sv | 2 +- src/riscv_asm_program_gen.sv | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/isa/riscv_instr.sv b/src/isa/riscv_instr.sv index f44e972a..0622583a 100644 --- a/src/isa/riscv_instr.sv +++ b/src/isa/riscv_instr.sv @@ -154,7 +154,7 @@ class riscv_instr extends uvm_object; if (!cfg.no_ebreak) begin basic_instr = {basic_instr, EBREAK}; foreach (riscv_instr_pkg::supported_isa[i]) begin - if (RV32C inside {riscv_instr_pkg::supported_isa[i]} && + if ( !cfg.disable_compressed_instr) begin basic_instr = {basic_instr, C_EBREAK}; break; diff --git a/src/riscv_asm_program_gen.sv b/src/riscv_asm_program_gen.sv index 6345239c..066dcad4 100644 --- a/src/riscv_asm_program_gen.sv +++ b/src/riscv_asm_program_gen.sv @@ -527,7 +527,6 @@ class riscv_asm_program_gen extends uvm_object; bit [DATA_WIDTH-1:0] reg_val; // Init general purpose registers with random values for(int i = 0; i < NUM_GPR; i++) begin - if (i inside {cfg.sp, cfg.tp}) continue; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(reg_val, reg_val dist { 'h0 :/ 1,