From 0246ca369e6f5a43db3a47f8be909927ede78259 Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Mon, 7 Oct 2024 16:27:24 +0200
Subject: [PATCH] Add verilator commands to yaml

Signed-off-by: Ryszard Rozak <rrozak@antmicro.com>
---
 yaml/simulator.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/yaml/simulator.yaml b/yaml/simulator.yaml
index 76dd6f1e..3f00c04a 100644
--- a/yaml/simulator.yaml
+++ b/yaml/simulator.yaml
@@ -93,6 +93,14 @@
     cmd: >
       <DSIM> <sim_opts> -sv_seed <seed> -pli_lib <DSIM_LIB_PATH>/libuvm_dpi.so +acc+rwb -image image -work <out>/dsim
 
+- tool: verilator
+  compile:
+    cmd:
+      - "verilator --binary -I$RV_ROOT/tools/riscv-dv/ $UVM_DIR/uvm.sv -I$UVM_DIR -f $RISCV_DV_ROOT/files.f --timing -DUVM_NO_DPI -Wno-lint -Wno-style -Wno-CONSTRAINTIGN -Wno-ZERODLY -Wno-SYMRSVDWORD --build-jobs `nproc` --output-groups  50"
+  sim:
+    cmd: >
+      obj_dir/Vuvm
+
 - tool: qrun
   compile:
     cmd: