From afb08a36ccce7d39a3fbb261305c2323a53c0e93 Mon Sep 17 00:00:00 2001 From: Manar Date: Tue, 10 Nov 2020 19:26:28 +0200 Subject: [PATCH] Renamed lvs guard to use_power_pins - Also, added guard to the cells in the custom memory - dropped DLVS from the dv Makefiles --- verilog/dv/caravel/mgmt_soc/gpio/Makefile | 2 +- verilog/dv/caravel/mgmt_soc/hkspi/Makefile | 2 +- verilog/dv/caravel/mgmt_soc/mem/Makefile | 2 +- .../dv/caravel/mgmt_soc/mprj_ctrl/Makefile | 2 +- .../dv/caravel/mgmt_soc/pass_thru/Makefile | 2 +- verilog/dv/caravel/mgmt_soc/perf/Makefile | 2 +- verilog/dv/caravel/mgmt_soc/pll/Makefile | 2 +- verilog/dv/caravel/mgmt_soc/storage/Makefile | 2 +- verilog/dv/caravel/mgmt_soc/sysctrl/Makefile | 2 +- verilog/dv/caravel/mgmt_soc/timer/Makefile | 2 +- verilog/dv/caravel/mgmt_soc/timer2/Makefile | 2 +- verilog/dv/caravel/mgmt_soc/uart/Makefile | 2 +- .../user_proj_example/io_ports/Makefile | 2 +- .../user_proj_example/la_test1/Makefile | 2 +- .../user_proj_example/la_test2/Makefile | 2 +- verilog/rtl/DFFRAM.v | 102 +++- verilog/rtl/DFFRAMBB.v | 443 ++++++++++++++++-- verilog/rtl/caravel.v | 6 +- verilog/rtl/caravel_clocking.v | 2 +- verilog/rtl/digital_pll.v | 4 +- verilog/rtl/gpio_control_block.v | 2 +- verilog/rtl/housekeeping_spi.v | 4 +- verilog/rtl/mem_wb.v | 8 +- verilog/rtl/mgmt_core.v | 10 +- verilog/rtl/mgmt_soc.v | 4 +- verilog/rtl/sram_1rw1r_32_256_8_sky130.v | 4 +- 26 files changed, 511 insertions(+), 108 deletions(-) diff --git a/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/mgmt_soc/gpio/Makefile index 425e30898..49bbb0ccb 100644 --- a/verilog/dv/caravel/mgmt_soc/gpio/Makefile +++ b/verilog/dv/caravel/mgmt_soc/gpio/Makefile @@ -15,7 +15,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile index e286d648c..4a8b06675 100644 --- a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile +++ b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile @@ -16,7 +16,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/mem/Makefile b/verilog/dv/caravel/mgmt_soc/mem/Makefile index e21039522..49a3f73e9 100644 --- a/verilog/dv/caravel/mgmt_soc/mem/Makefile +++ b/verilog/dv/caravel/mgmt_soc/mem/Makefile @@ -16,7 +16,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile index a591f7505..b6c988915 100644 --- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile +++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile @@ -16,7 +16,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile index c2d83862b..a902f21a1 100644 --- a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile +++ b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile @@ -16,7 +16,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/perf/Makefile b/verilog/dv/caravel/mgmt_soc/perf/Makefile index b7642c123..4c2453394 100644 --- a/verilog/dv/caravel/mgmt_soc/perf/Makefile +++ b/verilog/dv/caravel/mgmt_soc/perf/Makefile @@ -15,7 +15,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/pll/Makefile b/verilog/dv/caravel/mgmt_soc/pll/Makefile index 24aa33cf4..4a5dfc8d1 100644 --- a/verilog/dv/caravel/mgmt_soc/pll/Makefile +++ b/verilog/dv/caravel/mgmt_soc/pll/Makefile @@ -15,7 +15,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(PDK_PATH) -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(PDK_PATH) -I $(BEHAVIOURAL_MODELS) \ -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/storage/Makefile b/verilog/dv/caravel/mgmt_soc/storage/Makefile index 386bc6536..c7ee60757 100644 --- a/verilog/dv/caravel/mgmt_soc/storage/Makefile +++ b/verilog/dv/caravel/mgmt_soc/storage/Makefile @@ -15,7 +15,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(PDK_PATH) -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(PDK_PATH) -I $(BEHAVIOURAL_MODELS) \ -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile index ab869e800..dd839515f 100644 --- a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile +++ b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile @@ -15,7 +15,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/timer/Makefile b/verilog/dv/caravel/mgmt_soc/timer/Makefile index cf236133f..4a67c440e 100644 --- a/verilog/dv/caravel/mgmt_soc/timer/Makefile +++ b/verilog/dv/caravel/mgmt_soc/timer/Makefile @@ -15,7 +15,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/timer2/Makefile b/verilog/dv/caravel/mgmt_soc/timer2/Makefile index b358627f4..3feaad758 100644 --- a/verilog/dv/caravel/mgmt_soc/timer2/Makefile +++ b/verilog/dv/caravel/mgmt_soc/timer2/Makefile @@ -15,7 +15,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -Wall -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -Wall -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/mgmt_soc/uart/Makefile b/verilog/dv/caravel/mgmt_soc/uart/Makefile index 31172dae4..cde1104c4 100644 --- a/verilog/dv/caravel/mgmt_soc/uart/Makefile +++ b/verilog/dv/caravel/mgmt_soc/uart/Makefile @@ -16,7 +16,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile index 438fb0ede..0f0482bc7 100644 --- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile +++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile @@ -15,7 +15,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/user_proj_example/la_test1/Makefile b/verilog/dv/caravel/user_proj_example/la_test1/Makefile index e37a3b05e..a258d8c23 100644 --- a/verilog/dv/caravel/user_proj_example/la_test1/Makefile +++ b/verilog/dv/caravel/user_proj_example/la_test1/Makefile @@ -15,7 +15,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/dv/caravel/user_proj_example/la_test2/Makefile b/verilog/dv/caravel/user_proj_example/la_test2/Makefile index 4bd5d6988..1b3823c86 100644 --- a/verilog/dv/caravel/user_proj_example/la_test2/Makefile +++ b/verilog/dv/caravel/user_proj_example/la_test2/Makefile @@ -15,7 +15,7 @@ all: ${PATTERN:=.vcd} hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -DFUNCTIONAL -DLVS -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v index 24f78e869..0607a186e 100644 --- a/verilog/rtl/DFFRAM.v +++ b/verilog/rtl/DFFRAM.v @@ -1,7 +1,7 @@ `ifndef USE_CUSTOM_DFFRAM module DFFRAM( -`ifdef LVS +`ifdef USE_POWER_PINS input VPWR, input VGND, `endif @@ -31,14 +31,16 @@ endmodule module DFFRAM #( parameter COLS=1, parameter ROWS=4) ( +`ifdef USE_POWER_PINS + VPWR, + VGND, +`endif CLK, WE, EN, Di, Do, - A, - VPWR, - VGND + A ); input CLK; @@ -48,9 +50,11 @@ module DFFRAM #( parameter COLS=1, parameter ROWS=4) output [31:0] Do; input [7:0] A; +`ifdef USE_POWER_PINS input VPWR; input VGND; - +`endif + wire [31:0] Di_buf; wire [31:0] Do_pre; wire CLK_buf; @@ -63,20 +67,80 @@ module DFFRAM #( parameter COLS=1, parameter ROWS=4) wire [3:0] row_sel; - sky130_fd_sc_hd__clkbuf_8 CLKBUF ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(CLK_buf), .A(CLK)); - sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(WE_buf), .A(WE)); - sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(Di_buf), .A(Di)); - - DEC2x4 DEC ( .VPWR(VPWR), .VGND(VGND), .EN(EN), .A(A[7:6]), .SEL(row_sel) ); - - SRAM64x32 B_0_0 ( .VPWR(VPWR), .VGND(VGND), .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A(A[5:0]) ); - SRAM64x32 B_0_1 ( .VPWR(VPWR), .VGND(VGND), .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A(A[5:0]) ); - SRAM64x32 B_0_2 ( .VPWR(VPWR), .VGND(VGND), .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A(A[5:0]) ); - SRAM64x32 B_0_3 ( .VPWR(VPWR), .VGND(VGND), .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A(A[5:0]) ); - - MUX4x1_32 MUX1 ( .VPWR(VPWR), .VGND(VGND), .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A[7:6]), .X(Do_pre) ); - - sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(Do), .A(Do_pre)); + sky130_fd_sc_hd__clkbuf_8 CLKBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(CLK_buf), + .A(CLK) + ); + + sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(WE_buf), + .A(WE) + ); + + sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(Di_buf), + .A(Di) + ); + + DEC2x4 DEC ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), .VGND(VGND), + `endif + .EN(EN), .A(A[7:6]), .SEL(row_sel) ); + + SRAM64x32 B_0_0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[0]), .Di(Di_buf), .Do(Do_B_0_0), .A(A[5:0]) ); + SRAM64x32 B_0_1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[1]), .Di(Di_buf), .Do(Do_B_0_1), .A(A[5:0]) ); + SRAM64x32 B_0_2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[2]), .Di(Di_buf), .Do(Do_B_0_2), .A(A[5:0]) ); + SRAM64x32 B_0_3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf), .EN(row_sel[3]), .Di(Di_buf), .Do(Do_B_0_3), .A(A[5:0]) ); + + MUX4x1_32 MUX1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), .VGND(VGND), + `endif + .A0(Do_B_0_0), .A1(Do_B_0_1), .A2(Do_B_0_2), .A3(Do_B_0_3), .S(A[7:6]), .X(Do_pre) ); + + sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(Do), .A(Do_pre)); endmodule diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v index 12eb781be..abe1f4486 100644 --- a/verilog/rtl/DFFRAMBB.v +++ b/verilog/rtl/DFFRAMBB.v @@ -6,13 +6,15 @@ */ module BYTE ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif input CLK, input WE, input SEL, input [7:0] Di, - output [7:0] Do, - input VPWR, - input VGND + output [7:0] Do ); wire [7:0] q_wire; @@ -20,15 +22,66 @@ module BYTE ( wire SEL_B; wire GCLK; - sky130_fd_sc_hd__inv_1 INV( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .Y(SEL_B), .A(SEL)); - sky130_fd_sc_hd__and2_1 CGAND( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .A(SEL), .B(WE), .X(we_wire) ); - sky130_fd_sc_hd__dlclkp_1 CG( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) ); + sky130_fd_sc_hd__inv_1 INV( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(SEL_B), + .A(SEL) + ); + + sky130_fd_sc_hd__and2_1 CGAND( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(SEL), + .B(WE), + .X(we_wire) + ); + + sky130_fd_sc_hd__dlclkp_1 CG( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .CLK(CLK), + .GCLK(GCLK), + .GATE(we_wire) + ); generate genvar i; for(i=0; i<8; i=i+1) begin : BIT - sky130_fd_sc_hd__dfxtp_1 FF ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) ); - sky130_fd_sc_hd__ebufn_2 OBUF ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) ); + sky130_fd_sc_hd__dfxtp_1 FF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .D(Di[i]), + .Q(q_wire[i]), + .CLK(GCLK) + ); + sky130_fd_sc_hd__ebufn_2 OBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(q_wire[i]), + .Z(Do[i]), + .TE_B(SEL_B) + ); end endgenerate @@ -36,91 +89,310 @@ endmodule module WORD32 ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif input CLK, input [3:0] WE, input SEL, input [31:0] Di, - output [31:0] Do, - input VPWR, - input VGND + output [31:0] Do ); - BYTE B0 ( .VPWR(VPWR), .VGND(VGND), .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) ); - BYTE B1 ( .VPWR(VPWR), .VGND(VGND), .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) ); - BYTE B2 ( .VPWR(VPWR), .VGND(VGND), .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) ); - BYTE B3 ( .VPWR(VPWR), .VGND(VGND), .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) ); + BYTE B0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK), + .WE(WE[0]), + .SEL(SEL), + .Di(Di[7:0]), + .Do(Do[7:0]) + ); + BYTE B1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK), + .WE(WE[1]), + .SEL(SEL), + .Di(Di[15:8]), + .Do(Do[15:8]) + ); + BYTE B2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK), + .WE(WE[2]), + .SEL(SEL), + .Di(Di[23:16]), + .Do(Do[23:16]) + ); + + BYTE B3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK), + .WE(WE[3]), + .SEL(SEL), + .Di(Di[31:24]), + .Do(Do[31:24]) + ); endmodule module DEC2x4 ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif input EN, input [1:0] A, - output [3:0] SEL, - input VPWR, - input VGND + output [3:0] SEL ); - sky130_fd_sc_hd__nor3b_2 AND0 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .Y(SEL[0]), .A(A[0]), .B(A[1]), .C_N(EN) ); - sky130_fd_sc_hd__and3b_2 AND1 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) ); - sky130_fd_sc_hd__and3b_2 AND2 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) ); - sky130_fd_sc_hd__and3_2 AND3 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(SEL[3]), .A(A[1]), .B(A[0]), .C(EN) ); + sky130_fd_sc_hd__nor3b_2 AND0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(SEL[0]), + .A(A[0]), + .B(A[1]), + .C_N(EN) + ); + sky130_fd_sc_hd__and3b_2 AND1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[1]), + .A_N(A[1]), + .B(A[0]), + .C(EN) + ); + + sky130_fd_sc_hd__and3b_2 AND2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[2]), + .A_N(A[0]), + .B(A[1]), + .C(EN) + ); + + sky130_fd_sc_hd__and3_2 AND3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[3]), + .A(A[1]), + .B(A[0]), + .C(EN) + ); endmodule module DEC3x8 ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif input EN, input [2:0] A, - output [7:0] SEL, - input VPWR, - input VGND + output [7:0] SEL ); - sky130_fd_sc_hd__nor4b_2 AND0 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .Y(SEL[0]) , .A(A[0]), .B(A[1]) , .C(A[2]), .D_N(EN) ); // 000 - sky130_fd_sc_hd__and4bb_2 AND1 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(SEL[1]) , .A_N(A[2]), .B_N(A[1]), .C(A[0]) , .D(EN) ); // 001 - sky130_fd_sc_hd__and4bb_2 AND2 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(SEL[2]) , .A_N(A[2]), .B_N(A[0]), .C(A[1]) , .D(EN) ); // 010 - sky130_fd_sc_hd__and4b_2 AND3 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(SEL[3]) , .A_N(A[2]), .B(A[1]), .C(A[0]) , .D(EN) ); // 011 - sky130_fd_sc_hd__and4bb_2 AND4 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(SEL[4]) , .A_N(A[0]), .B_N(A[1]), .C(A[2]) , .D(EN) ); // 100 - sky130_fd_sc_hd__and4b_2 AND5 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(SEL[5]) , .A_N(A[1]), .B(A[0]), .C(A[2]) , .D(EN) ); // 101 - sky130_fd_sc_hd__and4b_2 AND6 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(SEL[6]) , .A_N(A[0]), .B(A[1]), .C(A[2]) , .D(EN) ); // 110 - sky130_fd_sc_hd__and4_2 AND7 ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(SEL[7]) , .A(A[0]), .B(A[1]), .C(A[2]) , .D(EN) ); // 111 + sky130_fd_sc_hd__nor4b_2 AND0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(SEL[0]), + .A(A[0]), + .B(A[1]), + .C(A[2]), + .D_N(EN) + ); // 000 + + sky130_fd_sc_hd__and4bb_2 AND1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[1]), + .A_N(A[2]), + .B_N(A[1]), + .C(A[0]), + .D(EN) + ); // 001 + + sky130_fd_sc_hd__and4bb_2 AND2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[2]), + .A_N(A[2]), + .B_N(A[0]), + .C(A[1]), + .D(EN) + ); // 010 + + sky130_fd_sc_hd__and4b_2 AND3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[3]), + .A_N(A[2]), + .B(A[1]), + .C(A[0]), + .D(EN) + ); // 011 + + sky130_fd_sc_hd__and4bb_2 AND4 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[4]), + .A_N(A[0]), + .B_N(A[1]), + .C(A[2]), + .D(EN) + ); // 100 + + sky130_fd_sc_hd__and4b_2 AND5 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[5]), + .A_N(A[1]), + .B(A[0]), + .C(A[2]), + .D(EN) + ); // 101 + + sky130_fd_sc_hd__and4b_2 AND6 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[6]), + .A_N(A[0]), + .B(A[1]), + .C(A[2]), + .D(EN) + ); // 110 + + sky130_fd_sc_hd__and4_2 AND7 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[7]), + .A(A[0]), + .B(A[1]), + .C(A[2]), + .D(EN) + ); // 111 endmodule module DEC6x64 ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif input EN, input [5:0] A, - output [63:0] SEL, - input VPWR, - input VGND + output [63:0] SEL ); wire [7:0] SEL0_w ; - DEC3x8 DEC_L0 ( .VPWR(VPWR), .VGND(VGND), .EN(EN), .A(A[5:3]), .SEL(SEL0_w) ); + DEC3x8 DEC_L0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(EN), .A(A[5:3]), .SEL(SEL0_w) ); generate genvar i; for(i=0; i<8; i=i+1) begin : DEC_L1 - DEC3x8 U ( .VPWR(VPWR), .VGND(VGND), .EN(SEL0_w[i]), .A(A[2:0]), .SEL(SEL[7+8*i: 8*i]) ); + DEC3x8 U ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(SEL0_w[i]), .A(A[2:0]), .SEL(SEL[7+8*i: 8*i]) ); end endgenerate endmodule module MUX4x1_32( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif input [31:0] A0, A1, A2, A3, input [1:0] S, - output [31:0] X, - input VPWR, - input VGND + output [31:0] X ); - sky130_fd_sc_hd__mux4_1 MUX[31:0] ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) ); + sky130_fd_sc_hd__mux4_1 MUX[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) ); endmodule module SRAM64x32( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif input CLK, input [3:0] WE, input EN, input [31:0] Di, output [31:0] Do, - input [5:0] A, - input VPWR, - input VGND + input [5:0] A ); wire [63:0] SEL; @@ -129,26 +401,93 @@ module SRAM64x32( wire CLK_buf; wire [3:0] WE_buf; - sky130_fd_sc_hd__clkbuf_16 CLKBUF ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(CLK_buf), .A(CLK)); - sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(WE_buf), .A(WE)); - sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .X(Di_buf), .A(Di)); + sky130_fd_sc_hd__clkbuf_16 CLKBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(CLK_buf), + .A(CLK) + ); + + sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(WE_buf), + .A(WE) + ); + + sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(Di_buf), + .A(Di) + ); - DEC6x64 DEC ( .VPWR(VPWR), .VGND(VGND), .EN(EN), .A(A), .SEL(SEL) ); + DEC6x64 DEC ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(EN), + .A(A), + .SEL(SEL) + ); generate genvar i; for (i=0; i< 64; i=i+1) begin : WORD - WORD32 W ( .VPWR(VPWR), .VGND(VGND), .CLK(CLK_buf), .WE(WE_buf), .SEL(SEL[i]), .Di(Di_buf), .Do(Do_pre) ); + WORD32 W ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK_buf), + .WE(WE_buf), + .SEL(SEL[i]), + .Di(Di_buf), + .Do(Do_pre) + ); end endgenerate // Ensure that the Do_pre lines are not floating when EN = 0 - sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .A({32{EN}}), .Z(Do_pre), .TE_B({32{EN}}) ); + sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A({32{EN}}), + .Z(Do_pre), + .TE_B({32{EN}}) + ); generate //genvar i; for(i=0; i<32; i=i+1) begin : OUT - sky130_fd_sc_hd__dfxtp_1 FF ( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND), .D(Do_pre[i]), .Q(Do[i]), .CLK(CLK) ); + sky130_fd_sc_hd__dfxtp_1 FF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .D(Do_pre[i]), + .Q(Do[i]), + .CLK(CLK) + ); end endgenerate diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index f3abb74f3..24a2f3fc6 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -332,7 +332,7 @@ module caravel ( wire [31:0] mgmt_rdata_ro; mgmt_core soc ( - `ifdef LVS + `ifdef USE_POWER_PINS .vdd1v8(vccd), .vss(vssa), `endif @@ -512,7 +512,7 @@ module caravel ( .DM_INIT(3'b110), // Mode = output, strong up/down .OENB_INIT(1'b1) // Enable output signaling from wire ) gpio_control_bidir [1:0] ( - `ifdef LVS + `ifdef USE_POWER_PINS .vccd(vccd), .vssd(vssd), .vccd1(vccd1), @@ -553,7 +553,7 @@ module caravel ( ); gpio_control_block gpio_control_in [`MPRJ_IO_PADS-1:2] ( - `ifdef LVS + `ifdef USE_POWER_PINS .vccd(vccd), .vssd(vssd), .vccd1(vccd1), diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v index ecf82157e..1b1555fc2 100644 --- a/verilog/rtl/caravel_clocking.v +++ b/verilog/rtl/caravel_clocking.v @@ -1,7 +1,7 @@ // This routine synchronizes the module caravel_clocking( -`ifdef LVS +`ifdef USE_POWER_PINS input vdd1v8, input vss, `endif diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v index 77cce4260..06ceaf98d 100644 --- a/verilog/rtl/digital_pll.v +++ b/verilog/rtl/digital_pll.v @@ -5,13 +5,13 @@ `include "ring_osc2x13.v" module digital_pll( -`ifdef LVS +`ifdef USE_POWER_PINS vdd, vss, `endif resetb, enable, osc, clockp, div, dco, ext_trim); -`ifdef LVS +`ifdef USE_POWER_PINS input vdd; input vss; `endif diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v index 681da94d5..bca5aa337 100644 --- a/verilog/rtl/gpio_control_block.v +++ b/verilog/rtl/gpio_control_block.v @@ -43,7 +43,7 @@ module gpio_control_block #( parameter ASEL_INIT = 1'b0, parameter APOL_INIT = 1'b0 ) ( - `ifdef LVS + `ifdef USE_POWER_PINS inout vccd, inout vssd, inout vccd1, diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v index 2942b2744..cc8d5d007 100644 --- a/verilog/rtl/housekeeping_spi.v +++ b/verilog/rtl/housekeeping_spi.v @@ -48,7 +48,7 @@ //------------------------------------------------------------ module housekeeping_spi( -`ifdef LVS +`ifdef USE_POWER_PINS vdd, vss, `endif RSTB, SCK, SDI, CSB, SDO, sdo_enb, @@ -61,7 +61,7 @@ module housekeeping_spi( pass_thru_user_sdi, pass_thru_user_sdo ); -`ifdef LVS +`ifdef USE_POWER_PINS inout vdd; // 3.3V supply inout vss; // common ground `endif diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v index 6e8799099..9a4abe323 100644 --- a/verilog/rtl/mem_wb.v +++ b/verilog/rtl/mem_wb.v @@ -1,5 +1,5 @@ module mem_wb ( -`ifdef LVS +`ifdef USE_POWER_PINS input VPWR, input VGND, `endif @@ -57,7 +57,7 @@ module mem_wb ( ) `endif mem ( - `ifdef LVS + `ifdef USE_POWER_PINS .VPWR(VPWR), .VGND(VGND), `endif @@ -79,7 +79,7 @@ module soc_mem ) `endif ( -`ifdef LVS +`ifdef USE_POWER_PINS input VPWR, input VGND, `endif @@ -93,7 +93,7 @@ module soc_mem `ifndef USE_OPENRAM DFFRAM SRAM ( - `ifdef LVS + `ifdef USE_POWER_PINS .VPWR(VPWR), .VGND(VGND), `endif diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v index 767a37748..50043c41f 100644 --- a/verilog/rtl/mgmt_core.v +++ b/verilog/rtl/mgmt_core.v @@ -1,5 +1,5 @@ module mgmt_core ( -`ifdef LVS +`ifdef USE_POWER_PINS inout vdd1v8, inout vss, `endif @@ -106,7 +106,7 @@ module mgmt_core ( assign jtag_out = (jtag_oenb_state == 1'b0) ? mgmt_out_data[0] : jtag_out_pre; caravel_clocking clocking( - `ifdef LVS + `ifdef USE_POWER_PINS .vdd1v8(vdd1v8), .vss(vss), `endif @@ -150,7 +150,7 @@ module mgmt_core ( // in the control block. mgmt_soc soc ( - `ifdef LVS + `ifdef USE_POWER_PINS .vdd1v8(vdd1v8), .vss(vss), `endif @@ -240,7 +240,7 @@ module mgmt_core ( ); digital_pll pll ( - `ifdef LVS + `ifdef USE_POWER_PINS .vdd(vdd1v8), .vss(vss), `endif @@ -255,7 +255,7 @@ module mgmt_core ( // Housekeeping SPI (SPI slave module) housekeeping_spi housekeeping ( - `ifdef LVS + `ifdef USE_POWER_PINS .vdd(vdd1v8), .vss(vss), `endif diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v index 4f26b40d6..df81c2ced 100644 --- a/verilog/rtl/mgmt_soc.v +++ b/verilog/rtl/mgmt_soc.v @@ -44,7 +44,7 @@ `include "convert_gpio_sigs.v" module mgmt_soc ( -`ifdef LVS +`ifdef USE_POWER_PINS inout vdd1v8, /* 1.8V domain */ inout vss, `endif @@ -735,7 +735,7 @@ module mgmt_soc ( wire [31:0] mem_dat_o; mem_wb soc_mem ( - `ifdef LVS + `ifdef USE_POWER_PINS .VPWR(vdd1v8), .VGND(vss), `endif diff --git a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v index 72864b16a..67f6baace 100644 --- a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v +++ b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v @@ -4,7 +4,7 @@ // Write size: 8 module sram_1rw1r_32_256_8_sky130( -`ifdef LVS +`ifdef USE_POWER_PINS vdd, gnd, `endif @@ -21,7 +21,7 @@ module sram_1rw1r_32_256_8_sky130( // FIXME: This delay is arbitrary. parameter DELAY = 3 ; -`ifdef LVS +`ifdef USE_POWER_PINS inout vdd; inout gnd; `endif