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the SLOT_WIDTH in axi_i2s_adi #842
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When I set the SLOT_WIDTH as 32, error comes.
The Error reported by Vivado:
[Synth 8-549] port width mismatch for port 'out_data': port width = 24, actual width = 32 [axi_i2s_adi.vhd":236]
The code statements in axi_i2s_adi.vhd are as follows:
The width of
outdata
is defined by FIFO_DWIDTH which always is 24, however, of thetx_data
, is defined by SLOT_WIDTH.According to the tcl file, the SLOT_WIDTH can be 16, 20, 24, 32. Is it right that just fit tx_data witdh to out_data like the s_axis_tdata does?
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