Can you simulate a purely combinatorial module in Amaranth

[TarikHamedovic]

I have a module that is just comb and when I try to simulate it in the Amaranth simulator it gets stuck without printing anything.
Can you simulate a combinatorial module? Also can you create something akin a Verilog function that also has no clock?

Here is the code:

from amaranth import *
from amaranth.sim import *

class Sqrt(Elaboratable):
    def __init__(self):
        self.num = Signal(32)     # Input signal
        self.sqrt = Signal(16)    # Output signal
        self.a = Signal(32)       # Internal signals for debugging
        self.q = Signal(16)
        self.left = Signal(signed(18))
        self.right = Signal(signed(18))
        self.r = Signal(signed(18))
        self.i = Signal(4)        # For loop counter

    def elaborate(self, platform):
        m = Module()


        with m.FSM() as fsm:
            with m.State("INIT"):
                m.d.comb += [
                    self.a.eq(self.num),
                    self.q.eq(0),
                    self.i.eq(0),
                    self.left.eq(0),
                    self.right.eq(0),
                    self.r.eq(0)
                ]
                m.next = "CALCULATE"

            with m.State("CALCULATE"):
                with m.If(self.i < 16):
                    m.d.comb += [
                        self.right.eq(Cat(1, self.r[17], self.q)),
                        self.left.eq(Cat(self.a[30:32], self.r[0:16])),
                        self.a.eq(self.a << 2)  # Left shift by 2 bits
                    ]
                    with m.If(self.r[17] == 1):  # Add if r is negative
                        m.d.comb += self.r.eq(self.left + self.right)
                    with m.Else():  # Subtract if r is positive
                        m.d.comb += self.r.eq(self.left - self.right)
                    m.d.comb += [
                        self.q.eq(Cat(~self.r[17], self.q[0:15])),
                        self.i.eq(self.i + 1)
                    ]
                with m.Else():
                    m.d.comb += self.sqrt.eq(self.q)
                    m.next = "DONE"

            with m.State("DONE"):
                pass  # End of FSM

        return m

class Top(Elaboratable):
    def __init__(self):
        self.num = Signal(32)
        self.sqrt = Signal(16)

    def elaborate(self, platform):
        m = Module()

        self.sqrt_module = Sqrt()
        m.submodules.sqrt_module = self.sqrt_module

        m.d.comb += [
            self.sqrt_module.num.eq(self.num),
            self.sqrt.eq(self.sqrt_module.sqrt)
        ]

        return m

# Simulate the top-level module
if __name__ == "__main__":
    from amaranth.back import verilog
    from amaranth.sim import Simulator

    top = Top()

    sim = Simulator(top)
    sim.add_clock(1e-6)  # Add a 1 MHz clock

    def process():
        yield top.num.eq(127)  
        #yield Tick()
        for _ in range(17):
            yield Tick()
            a = yield top.sqrt_module.a
            q = yield top.sqrt_module.q
            left = yield top.sqrt_module.left
            right = yield top.sqrt_module.right
            r = yield top.sqrt_module.r
            i = yield top.sqrt_module.i
            print(f"Iteration {i}: a={a}, q={q}, left={left}, right={right}, r={r}")

        result = yield top.sqrt
        print(f"Square root: {result}")

    sim.add_testbench(process)
    with sim.write_vcd("sqrt.vcd", "sqrt.gtkw"):
        sim.run()

[whitequark]

Take a look at the documentation page for the simulator on this topic.

[whitequark]

On second look, what you say is not accurate as the module is not fully combinational: an FSM inherently requires a clock, and m.next = ... is analogous to m.d.sync += next_state.eq(...)

[TarikHamedovic]

Hello,

I also tried with the tesbench instead of process and removed the FSM part. Now the circuit is combinational but when simulating I just get stuck at the beginning. Here is the updated code.
Am I missing something?

from amaranth import *
from amaranth.sim import *

class Sqrt(Elaboratable):
    def __init__(self):
        self.num = Signal(32)     # Input signal
        self.sqrt = Signal(16)    # Output signal
        self.a = Signal(32, init=0)       # Internal signals for debugging
        self.q = Signal(16)
        self.left = Signal(signed(18))
        self.right = Signal(signed(18))
        self.r = Signal(signed(18))

    def elaborate(self, platform):
        m = Module()

        a = Signal(32)
        q = Signal(16)
        left = Signal(signed(18))
        right = Signal(signed(18))
        r = Signal(signed(18))

        m.d.comb += [
            a.eq(self.num),
            q.eq(0),
            r.eq(0),
        ]

        for i in range(16):
            m.d.comb += [
                right.eq(Cat(1, r[17], q)),
                left.eq(Cat(a[30:32], r[0:16])),
                a.eq(a << 2)  # Left shift by 2 bits
            ]
            with m.If(r[17] == 1):  # Add if r is negative
                m.d.comb += r.eq(left + right)
            with m.Else():  # Subtract if r is positive
                m.d.comb += r.eq(left - right)
            m.d.comb += [
                q.eq(Cat(~r[17], q[0:15])),
            ]

        m.d.comb += self.sqrt.eq(q)

        return m

class Top(Elaboratable):
    def __init__(self):
        self.num = Signal(32)
        self.sqrt = Signal(16)

    def elaborate(self, platform):
        m = Module()

        self.sqrt_module = Sqrt()
        m.submodules.sqrt_module = self.sqrt_module

        m.d.comb += [
            self.sqrt_module.num.eq(self.num),
            self.sqrt.eq(self.sqrt_module.sqrt)
        ]

        return m

# Simulate the top-level module
if __name__ == "__main__":
    from amaranth.sim import Simulator

    top = Top()

    async def testbench(ctx):
        ctx.set(top.num, 121)
        await ctx.delay(10e-6)
        a = ctx.get(top.sqrt_module.a)
        q = ctx.get(top.sqrt_module.q)
        left = ctx.get(top.sqrt_module.left)
        right = ctx.get(top.sqrt_module.right)
        r = ctx.get(top.sqrt_module.r)
        result = ctx.get(top.sqrt)
        print(f"a={a}, q={q}, left={left}, right={right}, r={r}")
        print(f"Square root: {result}")

    sim = Simulator(top)
    sim.add_testbench(testbench)
    with sim.write_vcd("sqrt.vcd", "sqrt.gtkw"):
        sim.run()

[whitequark]

Your design contains a combinational loop:

m.d.comb += a.eq(a << 2)  # Left shift by 2 bits

This operation causes an infinite loop in simulation, and raises the following error if you try to do verilog.convert(Top(), pors=[]):

amaranth.hdl._nir.CombinationalCycle: Combinational cycle detected, path:
  /home/whitequark/Projects/amaranth/x.py:33: operator << bit 0
  /home/whitequark/Projects/amaranth/x.py:17: signal a bit 0
  /home/whitequark/Projects/amaranth/x.py:33: cell AssignmentList bit 0

[TarikHamedovic]

Just to update that I fixed the problem and thanks for the guidance. If anyone needs a square root module that works and is implemented entirely in the combinatorial domain here is the code:

from amaranth import *
from amaranth.sim import *
from amaranth.back import verilog

class sqrt_combinatorial(Elaboratable):
    def __init__(self, N=32):
        # Define the module's ports

        # Parameters
        self.N = N

        # Inputs
        self.num = Signal(N)         # Input: number to calculate the square root of

        # Outputs
        self.result = Signal(N // 2) # Output: calculated square root


    def elaborate(self, platform):
        """Elaborate the hardware description for the square root function."""
        
        m = Module()
        N = self.N
        
        # Arrays to hold intermediate values
        a = Array([Signal(N) for _ in range(N // 2 + 1)])
        q = Array([Signal(N // 2) for _ in range(N // 2 + 1)])
        left = Array([Signal(N // 2 + 2) for _ in range(N // 2)])
        right = Array([Signal(N // 2 + 2) for _ in range(N // 2)])
        r = Array([Signal(N // 2 + 2) for _ in range(N // 2 + 1)])

        # Initialize the first element
        m.d.comb += [a[0].eq(self.num), 
                     q[0].eq(0), 
                     r[0].eq(0)]

        # Generate the calculation steps
        for i in range(N // 2):
            m.d.comb += [

                right[i].eq(Cat(Const(1, 1), 
                                r[i][-1], 
                                q[i])),
                                
                left[i].eq(Cat(a[i][N - 2 : N], 
                               r[i][0 : N // 2])),

                a[i + 1].eq(a[i].shift_left(2)),
            ]

            with m.If(r[i][-1] == 1):
                m.d.comb += r[i + 1].eq(left[i] + right[i])
            with m.Else():
                m.d.comb += r[i + 1].eq(left[i] - right[i])

            m.d.comb += q[i + 1].eq(Cat(~(r[i + 1][-1]), 
                                        q[i][0 : N // 2 - 1]))

        # Assign the final result
        m.d.comb += self.result.eq(q[N // 2])

        return m