From b9417bb691827ff4020f804da3305ecaddbe668a Mon Sep 17 00:00:00 2001 From: Steven Kravatsky Date: Tue, 14 May 2024 17:32:39 -0400 Subject: [PATCH] Merged with altera-opensource u-boot-socfpga socfpga_v2023.10 branch Date: Tue May 14 17:25:38 2024 -0400 modified: arch/arm/dts/Makefile new file: arch/arm/dts/socfpga_agilex5_axe5_eagle-u-boot.dtsi new file: arch/arm/dts/socfpga_agilex5_axe5_eagle.dts modified: arch/arm/mach-socfpga/Kconfig new file: board/arrow/agilex5-axe5-eagle/MAINTAINERS new file: board/arrow/agilex5-axe5-eagle/Makefile new file: board/arrow/agilex5-axe5-eagle/socfpga.c new file: configs/socfpga_agilex5_axe5_eagle_defconfig new file: include/configs/socfpga_agilex5_axe5_eagle.h new file: include/socfpga_agilex5_axe5_eagle.h Signed-off-by: Steven Kravatsky --- arch/arm/dts/Makefile | 1 + .../socfpga_agilex5_axe5_eagle-u-boot.dtsi | 143 +++++++++++ arch/arm/dts/socfpga_agilex5_axe5_eagle.dts | 225 ++++++++++++++++++ arch/arm/mach-socfpga/Kconfig | 7 + board/arrow/agilex5-axe5-eagle/MAINTAINERS | 6 + board/arrow/agilex5-axe5-eagle/Makefile | 7 + board/arrow/agilex5-axe5-eagle/socfpga.c | 7 + configs/socfpga_agilex5_axe5_eagle_defconfig | 174 ++++++++++++++ include/configs/socfpga_agilex5_axe5_eagle.h | 12 + include/socfpga_agilex5_axe5_eagle.h | 12 + 10 files changed, 594 insertions(+) create mode 100644 arch/arm/dts/socfpga_agilex5_axe5_eagle-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_axe5_eagle.dts create mode 100644 board/arrow/agilex5-axe5-eagle/MAINTAINERS create mode 100644 board/arrow/agilex5-axe5-eagle/Makefile create mode 100644 board/arrow/agilex5-axe5-eagle/socfpga.c create mode 100644 configs/socfpga_agilex5_axe5_eagle_defconfig create mode 100644 include/configs/socfpga_agilex5_axe5_eagle.h create mode 100644 include/socfpga_agilex5_axe5_eagle.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index eb175daf802..4ec4635769a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -495,6 +495,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk_qspi.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex5_emu.dtb \ + socfpga_agilex5_axe5_eagle.dtb \ socfpga_agilex7m_socdk.dtb \ socfpga_agilex7m_socdk_nand.dtb \ socfpga_arria5_secu1.dtb \ diff --git a/arch/arm/dts/socfpga_agilex5_axe5_eagle-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_axe5_eagle-u-boot.dtsi new file mode 100644 index 00000000000..7e9e92fa034 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_axe5_eagle-u-boot.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2022-2023 Intel Corporation + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; + }; + + memory { + /* 1GB on Simics*/ + reg = <0 0x80000000 0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory"; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; + /delete-property/ cdns,read-delay; // sjk added +}; + +&flash1 { + bootph-all; +}; + +&i3c0 { + bootph-all; +}; + +&i3c1 { + bootph-all; +}; + +&mmc { + status = "okay"; + bus-width = <4>; + sd-uhs-sdr50; + cap-mmc-highspeed; + bootph-all; +}; + +&combophy0 { + status = "okay"; + bootph-all; + cdns,phy-use-ext-lpbk-dqs = <1>; + cdns,phy-use-lpbk-dqs = <1>; + cdns,phy-use-phony-dqs = <1>; + cdns,phy-use-phony-dqs-cmd = <1>; + cdns,phy-io-mask-always-on = <0>; + cdns,phy-io-mask-end = <5>; + cdns,phy-io-mask-start = <0>; + cdns,phy-data-select-oe-end = <1>; + cdns,phy-sync-method = <1>; + cdns,phy-sw-half-cycle-shift = <0>; + cdns,phy-rd-del-sel = <52>; + cdns,phy-underrun-suppress = <1>; + cdns,phy-gate-cfg-always-on = <1>; + cdns,phy-param-dll-bypass-mode = <1>; + cdns,phy-param-phase-detect-sel = <2>; + cdns,phy-param-dll-start-point = <254>; + cdns,phy-read-dqs-cmd-delay = <0>; + cdns,phy-clk-wrdqs-delay = <0>; + cdns,phy-clk-wr-delay = <0>; + cdns,phy-read-dqs-delay = <0>; + cdns,phy-phony-dqs-timing = <0>; + cdns,hrs09-rddata-en = <1>; + cdns,hrs09-rdcmd-en = <1>; + cdns,hrs09-extended-wr-mode = <1>; + cdns,hrs09-extended-rd-mode = <1>; + cdns,hrs10-hcsdclkadj = <3>; + cdns,hrs16-wrdata1-sdclk-dly = <0>; + cdns,hrs16-wrdata0-sdclk-dly = <0>; + cdns,hrs16-wrcmd1-sdclk-dly = <0>; + cdns,hrs16-wrcmd0-sdclk-dly = <0>; + cdns,hrs16-wrdata1-dly = <0>; + cdns,hrs16-wrdata0-dly = <0>; + cdns,hrs16-wrcmd1-dly = <0>; + cdns,hrs16-wrcmd0-dly = <0>; + cdns,hrs07-rw-compensate = <10>; + cdns,hrs07-idelay-val = <0>; +}; + +&qspi { + status = "okay"; +}; + +&nand { + bootph-all; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; + +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&fdt_0_blob { + filename = "arch/arm/dts/socfpga_agilex5_axe5_eagle.dtb"; +}; + +/* To add NAND dtb when ready in future */ + +&binman { + /delete-node/ kernel; +}; +#endif + diff --git a/arch/arm/dts/socfpga_agilex5_axe5_eagle.dts b/arch/arm/dts/socfpga_agilex5_axe5_eagle.dts new file mode 100644 index 00000000000..eacde9d0090 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_axe5_eagle.dts @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2023 Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 AXE5-Eagle"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet2 = &gmac2; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + // GPIO bank 0 pin 7 + gpios = <&porta 7 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + // GPIO bank 0 pin 8 + gpios = <&porta 8 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i3c0 { + status = "disabled"; +}; + +&i3c1 { + status = "disabled"; +}; + +&mmc { + status = "okay"; +}; + +&combophy0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb0 { + status = "disabled"; + disable-over-current; +}; + +&usb31 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&watchdog2 { + status = "okay"; +}; + +&watchdog3 { + status = "okay"; +}; + +&watchdog4 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&nand { + status = "disabled"; + + flash1: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "rootubi"; + reg = <0x200000 0x3fe00000>; + }; + }; +}; + +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mt25qu02g"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0BE00000>; + }; + }; + }; +}; + +&gmac0 { + status = "disabled"; + phy-mode = "rgmii"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 58f1bc612e8..3d2d38975ed 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -238,6 +238,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" select TARGET_SOCFPGA_AGILEX5 + +config TARGET_SOCFPGA_AGILEX5_AXE5_EAGLE + bool "Arrow SOCFPGA AXE5 EAGLE (Agilex5)" + select TARGET_SOCFPGA_AGILEX5 config TARGET_SOCFPGA_AGILEX7_SOCDK bool "Intel SOCFPGA SoCDK (Agilex7)" @@ -318,6 +322,7 @@ endchoice config SYS_BOARD default "agilex7-socdk" if TARGET_SOCFPGA_AGILEX7_SOCDK default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK + default "agilex5-axe5-eagle" if TARGET_SOCFPGA_AGILEX5_AXE5_EAGLE default "agilex-n6010" if TARGET_SOCFPGA_AGILEX_N6010 default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -351,6 +356,7 @@ config SYS_VENDOR default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK + default "arrow" if TARGET_SOCFPGA_AGILEX5_AXE5_EAGLE default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "google" if TARGET_SOCFPGA_CHAMELEONV3 @@ -373,6 +379,7 @@ config SYS_CONFIG_NAME default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK + default "socfpga_agilex5_axe5_eagle" if TARGET_SOCFPGA_AGILEX5_AXE5_EAGLE default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 diff --git a/board/arrow/agilex5-axe5-eagle/MAINTAINERS b/board/arrow/agilex5-axe5-eagle/MAINTAINERS new file mode 100644 index 00000000000..5cc7f63501a --- /dev/null +++ b/board/arrow/agilex5-axe5-eagle/MAINTAINERS @@ -0,0 +1,6 @@ +SOCFPGA BOARD +M: Steven Kravatsky +S: Maintained +F: board/arrow/agilex5-axe5-eagle/ +F: include/configs/socfpga_agilex5_axe5_eagle.h +F: configs/socfpga_agilex5_axe5_eagle_defconfig diff --git a/board/arrow/agilex5-axe5-eagle/Makefile b/board/arrow/agilex5-axe5-eagle/Makefile new file mode 100644 index 00000000000..52f7de88803 --- /dev/null +++ b/board/arrow/agilex5-axe5-eagle/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2022 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/arrow/agilex5-axe5-eagle/socfpga.c b/board/arrow/agilex5-axe5-eagle/socfpga.c new file mode 100644 index 00000000000..ae5c04557c8 --- /dev/null +++ b/board/arrow/agilex5-axe5-eagle/socfpga.c @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Intel Corporation + * + */ + +#include diff --git a/configs/socfpga_agilex5_axe5_eagle_defconfig b/configs/socfpga_agilex5_axe5_eagle_defconfig new file mode 100644 index 00000000000..66835246958 --- /dev/null +++ b/configs/socfpga_agilex5_axe5_eagle_defconfig @@ -0,0 +1,174 @@ +CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 +CONFIG_ARCH_SOCFPGA=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x04100000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_axe5_eagle" +CONFIG_SPL_MMC=y +CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS=y +CONFIG_TARGET_SOCFPGA_AGILEX5_AXE5_EAGLE=y +CONFIG_QPDS_HPS_HANDOFF=y +CONFIG_IDENT_STRING="socfpga_agilex5" +CONFIG_SPL_FS_FAT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x82000000 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" +CONFIG_LEGACY_IMAGE_FORMAT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_CRC32=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SYS_PROMPT="AXE5_EAGLE # " +CONFIG_CMD_NVEDIT_SELECT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_NOP_PHY=y +CONFIG_SPL_NOP_PHY=y +CONFIG_PHY_CADENCE_COMBOPHY=y +CONFIG_SPL_PHY_CADENCE_COMBOPHY=y +CONFIG_MMC=y +CONFIG_MMC_WRITE=y +# CONFIG_MMC_BROKEN_CD is not set +CONFIG_DM_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_MMC_SDHCI_ADMA_HELPERS=y +# CONFIG_ARM_PL180_MMCI is not set +CONFIG_MMC_QUIRKS=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=65535 +CONFIG_MMC_HW_PARTITIONING=y +# CONFIG_SUPPORT_EMMC_RPMB is not set +# CONFIG_SUPPORT_EMMC_BOOT is not set +# CONFIG_MMC_IO_VOLTAGE is not set +# CONFIG_MMC_HS400_ES_SUPPORT is not set +# CONFIG_MMC_HS400_SUPPORT is not set +# CONFIG_MMC_HS200_SUPPORT is not set +CONFIG_MMC_VERBOSE=n +CONFIG_MMC_TRACE=n +# CONFIG_MMC_DW is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_PCI is not set +# CONFIG_MMC_OMAP_HS is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_SDMA is not set +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +# CONFIG_MMC_SDHCI_BCMSTB is not set +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_CMD_FAT=y +CONFIG_DOS_PARTITION=y +CONFIG_SPL_DOS_PARTITION=y + +CONFIG_CMD_MTD=y +CONFIG_SPL_SYS_DCACHE_OFF=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_SPL_SPI_FLASH_MTD=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_MTDIDS_DEFAULT="nand0=10b80000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=10b80000.nand.0:2m(u-boot),-(root)" +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_LIST="" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_MISC_INIT_R=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_UBI_SILENCE_MSG=y +CONFIG_PHY_MARVELL=y +CONFIG_DM_ETH=y +CONFIG_DWC_ETH_XGMAC=y +CONFIG_RGMII=y +CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_UBIFS_SILENCE_MSG=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_WDT=y +CONFIG_CMD_WDT=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_SPL_WDT=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xbff00000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x73000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xbfa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_EFI_LOADER is not set +CONFIG_I3C=y +CONFIG_DW_I3C_MASTER=y +CONFIG_CMD_I3C=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_CADENCE=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_FRAMEWORK=y +CONFIG_SPL_NAND_CADENCE=y +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_TIMER=y +CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/include/configs/socfpga_agilex5_axe5_eagle.h b/include/configs/socfpga_agilex5_axe5_eagle.h new file mode 100644 index 00000000000..ad2b5632d1d --- /dev/null +++ b/include/configs/socfpga_agilex5_axe5_eagle.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019-2022 Intel Corporation + * + */ + +#ifndef __CONFIG_SOCFGPA_AGILEX5_H__ +#define __CONFIG_SOCFGPA_AGILEX5_H__ + +#include + +#endif /* __CONFIG_SOCFGPA_AGILEX5_H__ */ diff --git a/include/socfpga_agilex5_axe5_eagle.h b/include/socfpga_agilex5_axe5_eagle.h new file mode 100644 index 00000000000..ad2b5632d1d --- /dev/null +++ b/include/socfpga_agilex5_axe5_eagle.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019-2022 Intel Corporation + * + */ + +#ifndef __CONFIG_SOCFGPA_AGILEX5_H__ +#define __CONFIG_SOCFGPA_AGILEX5_H__ + +#include + +#endif /* __CONFIG_SOCFGPA_AGILEX5_H__ */