diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 3a3bc39bcd6..7696ae5747c 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -2474,6 +2474,7 @@ struct CxxrtlWorker {
 		RTLIL::Module *top_module = nullptr;
 		std::vector<RTLIL::Module*> modules;
 		TopoSort<RTLIL::Module*> topo_design;
+		bool has_prints = false;
 		for (auto module : design->modules()) {
 			if (!design->selected_module(module))
 				continue;
@@ -2486,6 +2487,8 @@ struct CxxrtlWorker {
 
 			topo_design.node(module);
 			for (auto cell : module->cells()) {
+				if (cell->type == ID($print))
+					has_prints = true;
 				if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
 					continue;
 				RTLIL::Module *cell_module = design->module(cell->type);
@@ -2544,6 +2547,8 @@ struct CxxrtlWorker {
 			f << "#include \"" << intf_filename << "\"\n";
 		else
 			f << "#include <backends/cxxrtl/cxxrtl.h>\n";
+		if (has_prints)
+			f << "#include <iostream>\n";
 		f << "\n";
 		f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
 		f << "    defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
diff --git a/tests/fmt/always_comb_tb.cc b/tests/fmt/always_comb_tb.cc
index f2a8c6b2695..5812500535a 100644
--- a/tests/fmt/always_comb_tb.cc
+++ b/tests/fmt/always_comb_tb.cc
@@ -1,4 +1,3 @@
-#include <iostream>
 #include "yosys-always_comb.cc"
 
 int main()
diff --git a/tests/fmt/always_full_tb.cc b/tests/fmt/always_full_tb.cc
index bd98020dec1..229f78aebe1 100644
--- a/tests/fmt/always_full_tb.cc
+++ b/tests/fmt/always_full_tb.cc
@@ -1,4 +1,3 @@
-#include <iostream>
 #include "yosys-always_full.cc"
 
 int main()
diff --git a/tests/fmt/display_lm_tb.cc b/tests/fmt/display_lm_tb.cc
index ebc62f80fad..7a593d72919 100644
--- a/tests/fmt/display_lm_tb.cc
+++ b/tests/fmt/display_lm_tb.cc
@@ -1,10 +1,9 @@
-#include <iostream>
 #include "yosys-display_lm.cc"
 
 int main()
 {
 	cxxrtl_design::p_top uut;
 
-    uut.step();
-    return 0;
+	uut.step();
+	return 0;
 }