From b453f61f07117e09928c8625fd9d4d5d53d90416 Mon Sep 17 00:00:00 2001 From: Daniel Roethlisberger Date: Fri, 27 Dec 2024 21:59:59 +0100 Subject: [PATCH] arm64: Lift FCVTZS Wd,Dn,#n to LLIL --- arch/arm64/arm64test.py | 4 ++++ arch/arm64/neon_intrinsics.cpp | 12 ++++++++++++ arch/arm64/neon_intrinsics.h | 1 + 3 files changed, 17 insertions(+) diff --git a/arch/arm64/arm64test.py b/arch/arm64/arm64test.py index 159d76af3..a24ac478f 100755 --- a/arch/arm64/arm64test.py +++ b/arch/arm64/arm64test.py @@ -3332,6 +3332,10 @@ (b'\x95\xFC\x7C\x5F', 'LLIL_INTRINSIC([d21],vcvtd_n_s64_f64,[LLIL_REG.q(d4),LLIL_CONST(4)])'), # fcvtzs d27, d5, #0x2f FCVTZS_asisdshf_C (b'\xBB\xFC\x51\x5F', 'LLIL_INTRINSIC([d27],vcvtd_n_s64_f64,[LLIL_REG.q(d5),LLIL_CONST(47)])'), + # fcvtzs w8, d0, #0x1b FCVTZS_32D_float2fix + (b'\x08\x94\x58\x1e', 'LLIL_INTRINSIC([w8],vcvtd_n_s32_f64,[LLIL_REG.q(d0),LLIL_CONST(27)])'), + # fcvtzs w9, d8, #0x0f FCVTZS_32D_float2fix + (b'\x09\xc5\x58\x1e', 'LLIL_INTRINSIC([w9],vcvtd_n_s32_f64,[LLIL_REG.q(d8),LLIL_CONST(15)])'), # fcvtzu w22, d30, #0x18 FCVTZU_32D_float2fix (b'\xD6\xA3\x59\x1E', 'LLIL_INTRINSIC([w22],vcvts_n_u32_f64,[LLIL_REG.q(d30),LLIL_CONST(24)])'), # fcvtzu w23, d16, #0x1d FCVTZU_32D_float2fix diff --git a/arch/arm64/neon_intrinsics.cpp b/arch/arm64/neon_intrinsics.cpp index e8a45503d..fdc5811ab 100644 --- a/arch/arm64/neon_intrinsics.cpp +++ b/arch/arm64/neon_intrinsics.cpp @@ -7930,6 +7930,8 @@ string NeonGetIntrinsicName(uint32_t intrinsic) return "vand_s64"; case ARM64_INTRIN_VCVTD_N_U64_F32: return "vcvtd_n_u64_f32"; + case ARM64_INTRIN_VCVTD_N_S32_F64: + return "vcvtd_n_s32_f64"; default: return ""; } @@ -17621,6 +17623,16 @@ bool NeonGetLowLevelILForInstruction( add_input_reg(inputs, il, instr.operands[1]); add_output_reg(outputs, il, instr.operands[0]); break; + case ENC_FCVTZS_32D_FLOAT2FIX: + if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[ 0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32)) + // int32_t vcvtd_n_s32_f64(float64_t a, const int n) + // argprep: a -> Dn, n -> n + // results: Wd -> result + intrin_id = ARM64_INTRIN_VCVTD_N_S32_F64; // FCVTZS Wd,Dn,#n + add_input_reg(inputs, il, instr.operands[1]); + add_input_imm(inputs, il, instr.operands[2]); + add_output_reg(outputs, il, instr.operands[0]); + break; case ENC_FCVTZS_32D_FLOAT2INT: if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31)) // int32_t vcvtd_s32_f64(float64_t a) diff --git a/arch/arm64/neon_intrinsics.h b/arch/arm64/neon_intrinsics.h index 087b8664f..8a8fe2f7b 100644 --- a/arch/arm64/neon_intrinsics.h +++ b/arch/arm64/neon_intrinsics.h @@ -3982,6 +3982,7 @@ enum NeonIntrinsic : uint32_t ARM64_INTRIN_VCVTS_N_U32_F64, ARM64_INTRIN_VCVTS_N_U64_F64, ARM64_INTRIN_VCVT_U64_F32, + ARM64_INTRIN_VCVTD_N_S32_F64, // The end, add more above ARM64_INTRIN_NEON_END };